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    Processor capable of executing programs that contain RISC and CISC instructions
    11.
    发明授权
    Processor capable of executing programs that contain RISC and CISC instructions 失效
    处理器能够执行包含RISC和CISC指令的程序

    公开(公告)号：US5638525A

    公开(公告)日：1997-06-10

    申请号：US386931

    申请日：1995-02-10

    申请人： Gary N. Hammond ,  Kevin C. Kahn ,  Donald B. Alpert

    发明人： Gary N. Hammond ,  Kevin C. Kahn ,  Donald B. Alpert

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/455

    CPC分类号： G06F9/3822 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/45533

    摘要： A data processor is described. The data processor is capable of decoding and executing the first instruction of a first instruction set and the second instruction of a second instruction set wherein the first instruction and the second instruction originate from a single computer program. Alternatively, the data processor can also execute a first instruction of a first instruction set in a first instruction set mode, receive a first interruption indication in the first instruction set mode, service the first interruption indication in a second instruction set mode, return to the first instruction set mode, receive a second interruption indication in the first instruction set mode, and service the second interruption indication in the first instruction set mode.

    摘要翻译： 描述数据处理器。 数据处理器能够解码和执行第一指令集的第一指令和第二指令集的第二指令，其中第一指令和第二指令源于单个计算机程序。 或者，数据处理器还可以以第一指令集模式执行第一指令集的第一指令，以第一指令集模式接收第一中断指示，以第二指令集模式服务第一中断指示，返回到 第一指令集模式，以第一指令集模式接收第二中断指示，并在第一指令集模式下服务第二中断指示。

    Input/output data processing system
    12.
    发明授权
    Input/output data processing system 失效
    输入/输出数据处理系统

    公开(公告)号：US4315310A

    公开(公告)日：1982-02-09

    申请号：US79991

    申请日：1979-09-28

    申请人： John A. Bayliss ,  George W. Cox ,  Bert E. Forbes ,  Kevin C. Kahn

    发明人： John A. Bayliss ,  George W. Cox ,  Bert E. Forbes ,  Kevin C. Kahn

    IPC分类号： G06F12/02 ,  G06F13/12 ,  G06F13/42 ,  G06F15/16 ,  G06F15/177 ,  G06F3/00

    CPC分类号： G06F12/0284 ,  G06F13/128 ,  G06F13/4208

    摘要： An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments.A function-request facility provides a functional capability over certain objects within the GDP address space.The two facilities provide software on an external processor with a window into the address space of the GDP that enables the software, via the function request means, to send messages to and receive messages from the GDP and to manipulate an environment provided for the external processor within its address space.

    摘要翻译： 一种用于在外围子系统和广义数据处理器之间提供接口的输入/输出处理器架构。 通过将I / O地址空间的一部分映射到GDP地址空间的一部分，接口处理器能够在两个地址空间（广义数据处理器地址空间和外部处理器I / O地址空间）之间传输数据。 该映射设施为外围子系统提供了一个“窗口”到相关的GDP子系统中。 它接受特定子范围内的地址或子范围，并将其转换为一个或多个GDP数据段的引用。 功能请求功能可以在GDP地址空间内的某些对象上提供功能。 这两个设施将外部处理器上的软件提供到GDP的地址空间中的窗口，使得软件能够通过功能请求装置向GDP发送消息并从其接收消息并且操纵为外部处理器提供的环境 在其地址空间内。

    Multi-processor programmable interrupt controller system
    14.
    发明授权
    Multi-processor programmable interrupt controller system 失效
    多处理器可编程中断控制器系统

    公开(公告)号：US5283904A

    公开(公告)日：1994-02-01

    申请号：US8074

    申请日：1993-01-22

    申请人： David G. Carson ,  Herman D. D'Hooge ,  Kevin C. Kahn

    发明人： David G. Carson ,  Herman D. D'Hooge ,  Kevin C. Kahn

    IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F13/26 ,  G06F15/00 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177

    CPC分类号： G06F13/26 ,  G06F15/17

    摘要： A multi-processor programmable interrupt controller system which includes: an I/O interrupt controller for receiving interrupt requests from an I/O subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for priority arbitration, using a standard message format and arbitration protocol.

    摘要翻译： 一种多处理器可编程中断控制器系统，包括：I / O中断控制器，用于从I / O子系统接收中断请求; 多个处理器中断控制器，每个与特定处理器相关联，用于分配接受的中断; 以及主要用于在中断控制器单元之间传输中断请求并且使用标准消息格式和仲裁协议进行优先级仲裁的中断控制器总线。

    Multi-protocol I/O interconnect architecture
    15.
    发明授权
    Multi-protocol I/O interconnect architecture 有权
    多协议I / O互连体系结构

    公开(公告)号：US09252970B2

    公开(公告)日：2016-02-02

    申请号：US13338222

    申请日：2011-12-27

    申请人： Prashant Chandra ,  Kevin C. Kahn

    发明人： Prashant Chandra ,  Kevin C. Kahn

    IPC分类号： H04L12/28 ,  H04L12/46

    CPC分类号： H04L12/4625

    摘要： Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for configuring a multi-protocol I/O interconnect may include identifying a plurality of switches of a switching fabric of a multi-protocol I/O interconnect, and configuring a path from a port of a first switch of the plurality of switches to a port of a second switch of the plurality of switches. Packets of a first protocol and packets of a second protocol, different from the first protocol, may be simultaneously routed over the path. Other embodiments may be described and claimed.

    摘要翻译： 描述了跨计算机设备的多协议I / O互连的多协议隧道传输的方法，装置和系统的实施例。 用于配置多协议I / O互连的方法可以包括识别多协议I / O互连的交换结构的多个交换机，以及配置从多个交换机的第一交换机的端口到 所述多个开关的第二开关的端口。 不同于第一协议的第一协议的分组和第二协议的分组可以在路径上同时路由。 可以描述和要求保护其他实施例。

    Physical address size selection and page size selection in an address translator
    17.
    发明授权
    Physical address size selection and page size selection in an address translator 失效
    地址翻译器中的物理地址大小选择和页面大小选择

    公开(公告)号：US5617554A

    公开(公告)日：1997-04-01

    申请号：US372805

    申请日：1994-12-23

    申请人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    发明人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1009 ,  G06F2212/652

    摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.

    摘要翻译： 这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。 可以选择不同的内存大小和不同的页面大小。 地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。 地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。 线性地址到字段的格式取决于所选的内存大小和所选的页面大小。 对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组 的页表条目。 表中条目的大小取决于所选的内存大小。 表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。

    System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer
    19.
    发明授权
    System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer 失效
    用于利用流水线控制切换执行DMA传输的系统，使得第一存储区域包含用于后续传送的缓冲器的位置

    公开(公告)号：US5828903A

    公开(公告)日：1998-10-27

    申请号：US751340

    申请日：1996-11-19

    申请人： Jay Sethuram ,  Haim Sadger ,  Kevin C. Kahn ,  Farhad Mighani

    发明人： Jay Sethuram ,  Haim Sadger ,  Kevin C. Kahn ,  Farhad Mighani

    IPC分类号： G06F13/28 ,  H04L12/56 ,  H04Q11/04 ,  G06F13/00

    CPC分类号： G06F13/28 ,  H04Q11/0478 ,  H04L2012/5652 ,  H04L2012/5681

    摘要： The present invention teaches a new system for transferring data between a network and hosts coupled to the network. The system uses an adapter, that is coupled between the host and the network, to allow segmenting and reassembling cells directly in the host memory. The present invention also teaches a pipelined DMA architecture to overcome the problem of the interruption of the DMA operation when switching from one virtual circuit to the next. This architecture depends on fast access to a local memory used for storing buffer descriptors for each virtual circuit. In this architecture, a two stage pipeline is used with the first stage performing the local memory access while the second stage performs the DMA transfers. When the pipeline is filled, both stages will operate in parallel yielding significant gain in performance due to continuous operation of the DMA.

    摘要翻译： 本发明教导了一种用于在网络和耦合到网络的主机之间传送数据的新系统。 该系统使用耦合在主机和网络之间的适配器，以允许在主机存储器中直接分割和重新组合单元。 本发明还教导了流水线DMA结构，以克服当从一个虚拟电路切换到下一个虚拟电路时DMA操作中断的问题。 该架构取决于快速访问用于存储每个虚拟电路的缓冲区描述符的本地存储器。 在该架构中，使用两级流水线，第一级执行本地存储器访问，而第二级执行DMA传输。 当管道填满时，由于DMA的连续运行，两个阶段将并行运行，从而产生显着的性能增益。

    Physical address size selection and page size selection in an address translator
    20.
    发明授权
    Physical address size selection and page size selection in an address translator 失效
    地址翻译器中的物理地址大小选择和页面大小选择

    公开(公告)号：US5802605A

    公开(公告)日：1998-09-01

    申请号：US756184

    申请日：1996-11-25

    申请人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    发明人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1009 ,  G06F2212/652

    摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.

    摘要翻译： 这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。 可以选择不同的内存大小和不同的页面大小。 地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。 地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。 线性地址到字段的格式取决于所选的内存大小和所选的页面大小。 对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组 的页表条目。 表中条目的大小取决于所选的内存大小。 表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。