公开(公告)号：US20160329976A1

公开(公告)日：2016-11-10

申请号：US14706917

申请日：2015-05-07

Applicant: QUALCOMM Incorporated

Inventor： Lai Kan Leung ,  Kevin Hsi Huai Wang ,  Dongling Pan ,  Chiewcharn Narathong

IPC: H04B17/21 ,  H03F3/21 ,  H03F3/19 ,  H04W24/02 ,  H03F1/02

CPC classification number: H04B17/21 ,  H03F1/0205 ,  H03F1/0277 ,  H03F3/189 ,  H03F3/19 ,  H03F3/211 ,  H03F3/24 ,  H03F3/62 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/21106 ,  H03F2203/21142 ,  H03F2203/21145 ,  H04W24/02

Abstract: An amplifier module with an output coupler is disclosed. The amplifier module may include a plurality of input terminals and two or more output terminals. Each input terminal may be coupled to an input of an independent amplifier. Outputs from the independent amplifiers may be coupled to the two or more output terminals. The amplifier module may include an output coupler to couple the two or more output terminals together. A signal may be received by a first output terminal and be coupled by the output coupler to a second output terminal. In some embodiments, when the two or more output terminals are coupled together, the independent amplifiers may be made inactive or operated in a minimum gain configuration.

Abstract translation: 公开了具有输出耦合器的放大器模块。 放大器模块可以包括多个输入端子和两个或更多个输出端子。 每个输入端可以耦合到独立放大器的输入。 来自独立放大器的输出可以耦合到两个或更多个输出端子。 放大器模块可以包括输出耦合器以将两个或多个输出端子耦合在一起。 信号可以由第一输出端子接收并且由输出耦合器耦合到第二输出端子。 在一些实施例中，当两个或更多个输出端子耦合在一起时，独立放大器可以被制成无效或以最小增益配置运行。

公开(公告)号：US09473336B2

公开(公告)日：2016-10-18

申请号：US14671939

申请日：2015-03-27

Applicant: QUALCOMM Incorporated

Inventor： Dongling Pan ,  Aleksandar Miodrag Tasic ,  Rajagopalan Rangarajan ,  Lai Kan Leung ,  Chiewcharn Narathong ,  Yiwu Tang

IPC: H04B7/00 ,  H04L27/06 ,  H04B1/10 ,  H04B7/26 ,  H04B1/00

CPC classification number: H04L27/063 ,  H04B1/005 ,  H04B1/10 ,  H04B7/26

Abstract: A radio frequency (RF) front end having multiple low noise amplifiers modules is disclosed. In an exemplary embodiment, an apparatus includes at least one first stage amplifier configured to amplify received carrier signals to generate at least one first stage carrier group. Each first stage carrier group includes a respective portion of the carrier signals. The apparatus also includes second stage amplifiers configured to amplify the first stage carrier groups. Each second stage amplifier configured to amplify a respective first stage carrier group to generate two second stage output signals that may be output to different demodulation stages where each demodulation stage demodulates a selected carrier signal.

Abstract translation: 公开了具有多个低噪声放大器模块的射频（RF）前端。 在示例性实施例中，装置包括至少一个第一级放大器，其配置成放大接收的载波信号以产生至少一个第一级载波组。 每个第一级载波组包括载波信号的相应部分。 该装置还包括配置成放大第一级载波组的第二级放大器。 每个第二级放大器被配置为放大相应的第一级载波组以产生两个第二级输出信号，其可以被输出到不同的解调级，其中每个解调级解调所选择的载波信号。

公开(公告)号：US09059733B2

公开(公告)日：2015-06-16

申请号：US13893099

申请日：2013-05-13

Applicant: QUALCOMM Incorporated

Inventor： Chiewcharn Narathong ,  Jong Min Park ,  Tsai-Pi Hung

IPC: H03M1/66 ,  H03L7/099 ,  H03G11/00 ,  H03L7/093 ,  H03B5/12 ,  H03M1/76

CPC classification number: H03M1/66 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03G11/008 ,  H03L7/093 ,  H03L7/099 ,  H03L2207/06 ,  H03M1/664 ,  H03M1/765

Abstract: A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.

Abstract translation: 电路包括具有用于将数字信号转换为模拟信号的非均匀分辨率的数模转换器。 数模转换器包括高分辨率电路，耦合到高分辨率电路的低分辨率电路和耦合到高分辨率电路和降低分辨率电路的开关。 该开关将高分辨率电路和降低分辨率电路之一耦合到输出节点。 电路还包括耦合到开关的解码器。 解码器接收数字信号以控制开关。

公开(公告)号：US20140273904A1

公开(公告)日：2014-09-18

申请号：US13828879

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Li Liu ,  Chiewcharn Narathong

IPC: H04B1/16

CPC classification number: H04B1/16 ,  H03L7/099 ,  H03L7/18

Abstract: Techniques for generating a local oscillator (LO) signal are disclosed. In one design, an apparatus includes an oscillator, a divider, and a phase locked loop (PLL). The oscillator receives a control signal and provides an oscillator signal having a frequency determined by the control signal. The divider receives the oscillator signal and generates multiple divided signals of different phases. The PLL receives a reference signal and a selected divided signal and generates the control signal for the oscillator. The divider is powered on and off periodically and wakes up in one of multiple possible states, with each state being associated with a different phase of the selected divided signal. Phase continuity of the selected divided signal is ensured by using the divider in a feedback loop with the PLL. The PLL locks the selected divided signal to the reference signal, and the selected divided signal has continuous phase due to the reference signal having continuous phase.

Abstract translation: 公开了用于产生本地振荡器（LO）信号的技术。 在一种设计中，装置包括振荡器，分频器和锁相环（PLL）。 振荡器接收控制信号并提供具有由控制信号确定的频率的振荡器信号。 分频器接收振荡器信号并产生不同相位的多个分频信号。 PLL接收参考信号和选择的分频信号，并产生振荡器的控制信号。 分频器周期性地通电和关断，并在多个可能状态之一中唤醒，每个状态与所选分频信号的不同相位相关联。 通过在与PLL的反馈环路中使用分频器来确保选择的分频信号的相位连续性。 PLL将所选择的分频信号锁定到参考信号，并且由于具有连续相位的参考信号，所选择的分频信号具有连续相位。

公开(公告)号：US20140134960A1

公开(公告)日：2014-05-15

申请号：US13677017

申请日：2012-11-14

Applicant: QUALCOMM INCORPORATED

Inventor： Aleksandar Miodrag Tasic ,  Anosh Bomi Davierwalla ,  Chiewcharn Narathong ,  Klaas van Zalinge

IPC: H04W88/02

CPC classification number: H04W88/02 ,  H03F3/193 ,  H03F3/68 ,  H04B1/0053

Abstract: Omni-band amplifiers supporting multiple band groups are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes at least one gain transistor and a plurality of cascode transistors for a plurality of band groups. Each band group covers a plurality of bands. The gain transistor(s) receive an input radio frequency (RF) signal. The cascode transistors are coupled to the gain transistor(s) and provide an output RF signal for one of the plurality of band groups. In an exemplary design, the gain transistor(s) include a plurality of gain transistors for the plurality of band groups. One gain transistor and one cascode transistor are enabled to amplify the input RF signal and provide the output RF signal for the selected band group. The gain transistors may be coupled to different taps of a single source degeneration inductor or to different source degeneration inductors.

Abstract translation: 公开了支持多个频带组的全频带放大器。 在示例性设计中，装置（例如，无线装置，集成电路等）包括用于多个频带组的至少一个增益晶体管和多个共源共栅晶体管。 每个带组覆盖多个频带。 增益晶体管接收输入射频（RF）信号。 共源共栅晶体管耦合到增益晶体管，并为多个带组中的一个提供输出RF信号。 在示例性设计中，增益晶体管包括用于多个带组的多个增益晶体管。 一个增益晶体管和一个共源共栅晶体管能够放大输入RF信号并提供所选频带组的输出RF信号。 增益晶体管可以耦合到单个源极退化电感器的不同抽头或不同的源极退化电感器。

公开(公告)号：US20140070899A1

公开(公告)日：2014-03-13

申请号：US13755130

申请日：2013-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Li Liu ,  Chiewcharn Narathong

IPC: H03B5/12 ,  H01L25/00

CPC classification number: H03B5/1228 ,  H01L25/00 ,  H01L2924/0002 ,  H03B5/04 ,  H03B5/1209 ,  H03B5/1243 ,  H03B2200/0088 ,  H03L1/00 ,  H03L7/099 ,  H01L2924/00

Abstract: A voltage controlled oscillator (VCO) core for cancelling a supply noise is described. The VCO core includes an input node that receives the supply noise. The VCO core also includes a noise path coupled to the input node. The VCO core additionally includes a cancellation path coupled to the input node and the noise path. The cancellation path includes a programmable gain circuit coupled with a first terminal of a varactor. The supply noise passes through the programmable gain circuit to produce a cancellation noise.

Abstract translation: 描述了用于消除电源噪声的压控振荡器（VCO）芯。 VCO核心包括接收电源噪声的输入节点。 VCO核心还包括耦合到输入节点的噪声路径。 VCO核心还包括耦合到输入节点和噪声路径的消除路径。 消除路径包括与变容二极管的第一端子耦合的可编程增益电路。 电源噪声通过可编程增益电路产生消除噪声。

公开(公告)号：US20130229954A1

公开(公告)日：2013-09-05

申请号：US13765992

申请日：2013-02-13

Applicant: QUALCOMM INCORPORATED

Inventor： Chiewcharn Narathong ,  Lai Kan Leung ,  Soon-Seng Lau ,  Shrenik Patel

IPC: H03B28/00

CPC classification number: H03B28/00 ,  H04B1/0475 ,  H04B1/406 ,  H04B1/408

Abstract: A dual frequency synthesizer architecture for a wireless device operating in a time division duplex (TDD) mode is disclosed. In an exemplary design, the wireless device includes first and second frequency synthesizers. The first frequency synthesizer generates a first oscillator signal used to generate a first/receive local oscillator (LO) signal at an LO frequency for the receiver. The second frequency synthesizer generates a second oscillator signal used to generate a second/transmit LO signal at the same LO frequency for the transmitter. The two frequency synthesizers generate their oscillator signals to obtain receive and transmit LO signals at the same LO frequency when the wireless device operates in the TDD mode.

Abstract translation: 公开了一种用于以时分双工（TDD）模式工作的无线设备的双频合成器架构。 在示例性设计中，无线设备包括第一和第二频率合成器。 第一频率合成器产生用于产生用于接收机的LO频率的第一/接收本地振荡器（LO）信号的第一振荡器信号。 第二频率合成器产生用于产生用于发射机的相同LO频率的第二/发射LO信号的第二振荡器信号。 当无线设备在TDD模式下工作时，两个频率合成器产生其振荡器信号以获得在相同LO频率下的接收和发送LO信号。

公开(公告)号：US11569865B1

公开(公告)日：2023-01-31

申请号：US17448872

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Chih-Fan Liao ,  Aleksandar Miodrag Tasic ,  Kyle David Holland ,  Jang Joon Lee ,  Jian Kang ,  Lai Kan Leung ,  Chiewcharn Narathong

IPC: H04B1/525

Abstract: Wireless signal processing may be improved by using a configurable baseband filter (BBF) in the receive path of a transceiver. A configurable BBF may accommodate processing of different wireless signals in a single integrated circuit (IC) chip. For example, a single IC may support processing of 5G mmWave RF signals and 5G sub-7 GHz RF signals by reconfiguring the BBF with settings appropriate for the different wireless signals. The reconfiguring of the BBF may include adjusting a bandwidth of the BBF and/or adjusting a filter order of the BBF. The reconfiguring of the BBF may be performed in response to detection of jammer signals to improve rejection of the jammer signals.

公开(公告)号：US09525503B2

公开(公告)日：2016-12-20

申请号：US14513003

申请日：2014-10-13

Applicant: QUALCOMM Incorporated

Inventor： Chiewcharn Narathong ,  Lai Kan Leung ,  Dongling Pan ,  Rajagopalan Rangarajan ,  Kevin Hsi-huai Wang ,  Bhushan Shanti Asuri ,  Yiwu Tang

IPC: H04J3/00 ,  H04J4/00 ,  H04W88/02 ,  H04B1/3827 ,  H04L5/14 ,  H04B1/00 ,  H04B1/403 ,  H04L5/00 ,  H04B1/50 ,  H04B1/54

CPC classification number: H04J4/00 ,  H04B1/0082 ,  H04B1/3833 ,  H04B1/403 ,  H04B1/50 ,  H04B1/54 ,  H04B7/00 ,  H04L5/001 ,  H04L5/0023 ,  H04L5/14 ,  H04L5/1469 ,  H04L7/00 ,  H04L27/36 ,  H04L27/38 ,  H04W88/02

Abstract: Reconfiguring a transceiver design using a plurality of frequency synthesizers and a plurality of carrier aggregation (CA) receiver (Rx) and transmitter (Tx) chains, the method including: connecting a first frequency synthesizer to a first CA Tx chain; connecting the plurality of frequency synthesizers to the plurality of CA Rx chains, wherein a second frequency synthesizer of the plurality of frequency synthesizers is connected as a shared synthesizer to a first CA Rx chain and a second CA Tx chain.

Abstract translation: 使用多个频率合成器和多个载波聚合（CA）接收机（Rx）和发射机（Tx）链重新配置收发器设计，所述方法包括：将第一频率合成器连接到第一CA Tx链; 将多个频率合成器连接到多个CA Rx链，其中多个频率合成器中的第二频率合成器作为共享合成器连接到第一CA Rx链和第二CA Tx链。

公开(公告)号：US09276622B2

公开(公告)日：2016-03-01

申请号：US13828879

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Li Liu ,  Chiewcharn Narathong

IPC: H04B1/16 ,  H03L7/18 ,  H03L7/099

CPC classification number: H04B1/16 ,  H03L7/099 ,  H03L7/18

Abstract: Techniques for generating a local oscillator (LO) signal are disclosed. In one design, an apparatus includes an oscillator, a divider, and a phase locked loop (PLL). The oscillator receives a control signal and provides an oscillator signal having a frequency determined by the control signal. The divider receives the oscillator signal and generates multiple divided signals of different phases. The PLL receives a reference signal and a selected divided signal and generates the control signal for the oscillator. The divider is powered on and off periodically and wakes up in one of multiple possible states, with each state being associated with a different phase of the selected divided signal. Phase continuity of the selected divided signal is ensured by using the divider in a feedback loop with the PLL. The PLL locks the selected divided signal to the reference signal, and the selected divided signal has continuous phase due to the reference signal having continuous phase.

Abstract translation: 公开了用于产生本地振荡器（LO）信号的技术。 在一种设计中，装置包括振荡器，分频器和锁相环（PLL）。 振荡器接收控制信号并提供具有由控制信号确定的频率的振荡器信号。 分频器接收振荡器信号并产生不同相位的多个分频信号。 PLL接收参考信号和选择的分频信号，并产生振荡器的控制信号。 分频器周期性地通电和关断，并在多个可能状态之一中唤醒，每个状态与所选分频信号的不同相位相关联。 通过在与PLL的反馈环路中使用分频器来确保选择的分频信号的相位连续性。 PLL将所选择的分频信号锁定到参考信号，并且由于具有连续相位的参考信号，所选择的分频信号具有连续相位。