公开(公告)号：US20170371797A1

公开(公告)日：2017-12-28

申请号：US15192984

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro OPORTUS VALENZUELA ,  Nieyan GENG ,  Gurvinder Singh CHHABRA ,  Richard SENIOR ,  Anand JANAKIRAMAN

IPC: G06F12/0877 ,  G06F12/0842

CPC classification number: G06F12/0877 ,  G06F12/023 ,  G06F12/0842 ,  G06F12/0855 ,  G06F12/0886 ,  G06F2212/1024 ,  G06F2212/401 ,  G06F2212/604 ,  H03M7/30

Abstract: Some aspects of the disclosure relate to a pre-fetch mechanism for a cache line compression system that increases RAM capacity and optimizes overflow area reads. For example, a pre-fetch mechanism may allow the memory controller to pipeline the reads from an area with fixed size slots (main compressed area) and the reads from an overflow area. The overflow area is arranged so that a cache line most likely containing the overflow data for a particular line may be calculated by a decompression engine. In this manner, the cache line decompression engine may fetch, in advance, the overflow area before finding the actual location of the overflow data.

公开(公告)号：US20170371792A1

公开(公告)日：2017-12-28

申请号：US15193001

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro OPORTUS VALENZUELA ,  Nieyan GENG ,  Christopher Edward KOOB ,  Gurvinder Singh CHHABRA ,  Richard SENIOR ,  Anand JANAKIRAMAN

IPC: G06F12/0871 ,  G06F12/0868

CPC classification number: G06F12/0871 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/281 ,  G06F2212/282 ,  G06F2212/313 ,  G06F2212/401 ,  G06F2212/601 ,  G06F2212/608

Abstract: In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in memory space left by the compression of high priority lines. The space left by the high priority lines and hence the low priority lines themselves are managed through pointers also stored in memory. In this manner, low priority lines contents can be moved to different memory locations as needed. The efficiency of higher priority compressed memory accesses is improved by removing the need for indirection otherwise required to find and access compressed memory lines, this is especially advantageous for immutable compressed contents. The use of pointers for low priority is advantageous due to the full flexibility of placement, especially for mutable compressed contents that may need movement within memory for instance as it changes in size over time

公开(公告)号：US20170063498A1

公开(公告)日：2017-03-02

申请号：US15237185

申请日：2016-08-15

Applicant: QUALCOMM Incorporated

Inventor： Ajay VENKATSURESH ,  Alok MITRA ,  Srinivas Reddy MUDIREDDY ,  Gurvinder Singh CHHABRA ,  Arnaud MEYLAN ,  Sirin NITINAWARAT ,  Vaibhav KUMAR ,  Sujit NAIR ,  Nehal SOMANI

IPC: H04L1/16 ,  H04L29/08

CPC classification number: H04L1/1635 ,  H04B3/50 ,  H04L1/1854 ,  H04L67/1097 ,  H04L69/16 ,  H04L69/326 ,  H04W28/0236

Abstract: A method, an apparatus, and a computer program product for transport protocol communications processing are provided. The apparatus may be an electronic device. The electronic device receives a transport protocol communications from a sender device. The electronic device generates a plurality of acknowledgments in response to the received transport protocol traffic and stores the plurality of acknowledgments at a first memory. A modem load for a modem of the electronic device is determined. The electronic device identifies the plurality of acknowledgments to identify a subset of the plurality of acknowledgments in response to the determined modem load satisfying a modem load threshold condition. The electronic device moves the subset of acknowledgments from the first memory to a second memory. The electronic device transmits the subset of acknowledgments to the sender device.

Abstract translation: 提供了一种用于传输协议通信处理的方法，装置和计算机程序产品。 该装置可以是电子装置。 电子设备从发送器设备接收传输协议通信。 电子设备响应于所接收的传输协议流量生成多个确认，并将多个确认存储在第一存储器中。 确定电子设备的调制解调器的调制解调器负载。 响应于满足调制解调器负载阈值条件的确定的调制解调器负载，电子设备识别多个确认以识别多个确认的子集。 电子设备将确认的子集从第一存储器移动到第二存储器。 电子设备将确认的子集发送给发送者设备。