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    TECHNIQUES FOR PACKET DATA CONVERGENCE PROTOCOL REORDERING WITHIN A TIMER
    2.
    发明公开
    TECHNIQUES FOR PACKET DATA CONVERGENCE PROTOCOL REORDERING WITHIN A TIMER 审中-公开

    公开(公告)号：US20240236009A1

    公开(公告)日：2024-07-11

    申请号：US18153105

    申请日：2023-01-11

    申请人： QUALCOMM Incorporated

    发明人： Arun Prasanth BALASUBRAMANIAN ,  Arnaud MEYLAN ,  Jason TAN ,  Shailesh MAHESHWARI

    IPC分类号： H04L47/34 ,  H04L47/28 ,  H04W28/10

    CPC分类号： H04L47/34 ,  H04L47/28 ,  H04W28/10

    摘要： Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a receiver device may receive a first packet of a plurality of packets included in a reordering window of the receiver device. The receiver device may receive a second packet of the plurality of packets. The receiver device may provide the first packet and the second packet based at least in part on expiration of a reordering timer. The receiver device may receive a third packet of the plurality of packets at a third time, wherein the first packet, the second packet, and the third packet are received sequentially. The receiver device may provide a set of packets including the first packet, the third packet, and the second packet in order, to a higher layer in accordance with a timer that is shorter than a length of the reordering window. Numerous other aspects are described.

    Managing A Reordering Timer
    6.
    发明申请
    Managing A Reordering Timer 有权

    公开(公告)号：US20210258409A1

    公开(公告)日：2021-08-19

    申请号：US17166244

    申请日：2021-02-03

    申请人： QUALCOMM Incorporated

    发明人： Sitaramanjaneyulu KANAMARLAPUDI ,  Arnaud MEYLAN

    IPC分类号： H04L29/06 ,  H04W76/28 ,  H04W72/04 ,  H04L1/08 ,  H04L12/861

    摘要： Embodiments include methods for managing a reordering timer performed by a processor of a wireless device. The processor may receive packets from a communication network and store the packets in a memory buffer of the wireless device. The processor may detect one or more conditions that affect an amount of time required to reorder or reassemble at least some of the packets received from the communication network. The processor may determine a timer adjustment based on the detected one or more conditions. The processor may adjust a timer with the determined timer adjustment. The processor may deliver one or more packets from the memory buffer in response to expiration of the adjusted timer.

    CQI-BASED DOWNLINK BUFFER MANAGEMENT
    8.
    发明申请
    CQI-BASED DOWNLINK BUFFER MANAGEMENT 有权

    公开(公告)号：US20210135727A1

    公开(公告)日：2021-05-06

    申请号：US16674724

    申请日：2019-11-05

    申请人： QUALCOMM Incorporated

    发明人： Ravi BALASUBRAMANIAN ,  Praveen ADUSUMILLI ,  Ammar KITABI ,  Arnaud MEYLAN

    IPC分类号： H04B7/06 ,  H04W24/10 ,  H04W28/02 ,  H04W28/06 ,  H04W72/08

    摘要： Certain aspects of the present disclosure provide techniques for channel quality indicator (CQI)-based downlink buffer management as well as mitigating throughput loss in dual connectivity with multi-SIM. A method that may be performed by a user equipment (UE) includes communicating with a first network on a first channel using a first technology, determining whether a tune-away associated with the first technology will occur, and outputting, for transmission to the first network on a second channel using a second technology, a channel quality indicator (CQI) report corresponding to the second channel if the tune-away will occur, wherein the CQI report indicates a lower CQI for the second channel than a current CQI for the second channel.