公开(公告)号：US20160350152A1

公开(公告)日：2016-12-01

申请号：US14866012

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GADELRAB ,  Christopher Edward KOOB ,  Simon BOOTH ,  Aris BALATSOS ,  Johnny Jone Wai KUAN ,  Myil RAMKUMAR ,  Bhupinder Singh PABLA ,  Sean David SWEENEY ,  George PATSILARAS

IPC: G06F9/48 ,  G06F11/07

CPC classification number: G06F9/4818 ,  G06F9/46 ,  G06F9/4887 ,  G06F11/0724 ,  G06F11/079 ,  G06F2209/506

Abstract: Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.

Abstract translation: 系统和方法涉及在包括两个或多个处理线程的多线程处理器中管理共享资源。 确定两个或更多个线程的危险水平，其中线程的危险等级基于线程由于不可用的共享资源而遇到期限的潜在故障。 还确定与两个或更多个线程相关联的优先级，其中对于不能达到期限的线程而言，优先级高于不能接受的线程，并且对于不满足截止期限的线程，优先级较低。 至少基于与两个或多个线程相关联的两个或多个线程的确定的危险等级和优先级，来调度两个或更多个线程。

公开(公告)号：US20160246534A1

公开(公告)日：2016-08-25

申请号：US14627433

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward KOOB ,  Erich James PLONDKE ,  Jiajin TU

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F1/32 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/30076 ,  G06F12/08 ,  G06F12/0888 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/502 ,  Y02D10/13

Abstract: Processor access of memory is monitored. The monitoring includes identifying the accesses being to a local memory or a non-local memory. Based on the monitoring, the processor is switched from a non-local memory access mode to a local memory access mode.

Abstract translation: 监视内存的处理器访问。 监视包括识别对本地存储器或非本地存储器的访问。 基于监视，处理器从非本地存储器访问模式切换到本地存储器访问模式。

公开(公告)号：US20160092238A1

公开(公告)日：2016-03-31

申请号：US14499044

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Lucian CODRESCU ,  Christopher Edward KOOB ,  Eric Wayne MAHURIN ,  Suresh Kumar VENKUMAHANTI

IPC: G06F9/38

CPC classification number: G06F9/3877 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F15/8053

Abstract: Systems and methods for implementing certain load instructions, such as vector load instructions by cooperation of a main processor and a coprocessor. The load instructions which are identified by the main processor for offloading to the coprocessor are committed in the main processor without receiving corresponding load data. Post-commit, the load instructions are processed in the coprocessor, such that latencies incurred in fetching the load data are hidden from the main processor. By implementing an out-of-order load data buffer associated with an in-order instruction buffer, the coprocessor is also configured to avoid stalls due to long latencies which may be involved in fetching the load data from levels of memory hierarchy, such as L2, L3, L4 caches, main memory, etc.

Abstract translation: 用于实现某些加载指令的系统和方法，例如通过主处理器和协处理器协作的向量加载指令。 由主处理器识别的用于卸载到协处理器的加载指令在主处理器中提交，而不接收相应的负载数据。 提交后，加载指令在协处理器中进行处理，这样在取出加载数据时产生的延迟从主处理器中隐藏起来。 通过实现与按顺序指令缓冲器相关联的无序负载数据缓冲器，协处理器还被配置为避免由于长时间延迟而导致的延迟，这可能涉及从诸如L2的存储器层级的级别中提取负载数据 ，L3，L4高速缓存，主内存等

公开(公告)号：US20170371792A1

公开(公告)日：2017-12-28

申请号：US15193001

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro OPORTUS VALENZUELA ,  Nieyan GENG ,  Christopher Edward KOOB ,  Gurvinder Singh CHHABRA ,  Richard SENIOR ,  Anand JANAKIRAMAN

IPC: G06F12/0871 ,  G06F12/0868

CPC classification number: G06F12/0871 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/281 ,  G06F2212/282 ,  G06F2212/313 ,  G06F2212/401 ,  G06F2212/601 ,  G06F2212/608

Abstract: In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in memory space left by the compression of high priority lines. The space left by the high priority lines and hence the low priority lines themselves are managed through pointers also stored in memory. In this manner, low priority lines contents can be moved to different memory locations as needed. The efficiency of higher priority compressed memory accesses is improved by removing the need for indirection otherwise required to find and access compressed memory lines, this is especially advantageous for immutable compressed contents. The use of pointers for low priority is advantageous due to the full flexibility of placement, especially for mutable compressed contents that may need movement within memory for instance as it changes in size over time

公开(公告)号：US20160246731A1

公开(公告)日：2016-08-25

申请号：US14626925

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward KOOB ,  Erich James PLONDKE ,  Jiajin TU

IPC: G06F12/10 ,  G06F11/07

CPC classification number: G06F12/1027 ,  G06F1/32 ,  G06F11/073 ,  G06F11/079 ,  G06F12/08 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/502 ,  G06F2212/684 ,  Y02D10/13

Abstract: A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.

Abstract translation: 翻译后备缓冲器（TLB）存储翻译条目。 翻译条目包括虚拟地址，物理地址和存储器本地/非本地标志。 当处理器处于低功耗/本地存储器模式时，接收到虚拟地址。 匹配的翻译条目具有本地/非本地标志。 在指示本地存储器外的匹配转换条目的物理地址的本地/非本地标志时，生成访问范围外存储器访问异常。