公开(公告)号：US11749327B2

公开(公告)日：2023-09-05

申请号：US17459186

申请日：2021-08-27

Applicant: QUALCOMM Incorporated

Inventor： Khaja Ahmad Shaik ,  Bharani Chava

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/16

CPC classification number: G11C11/005 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/419

Abstract: An exemplary memory bit cell circuit, including a bit line coupled to an SRAM bit cell circuit and an NVM bit cell circuit, with reduced area and reduced power consumption, included in a memory bit cell array circuit, is disclosed. The SRAM bit cell circuit includes cross-coupled true and complement inverters and a first access circuit coupled to the bit line. The NVM bit cell circuit includes an NVM device coupled to the bit line by a second access circuit and is coupled to the SRAM bit cell circuit. Data stored in the SRAM bit cell circuit and the NVM bit cell circuit are accessed based on voltages on the bit line. A true SRAM data is determined by an SRAM read voltage on the bit line, and an NVM data in the NVM bit cell circuit is determined by a first NVM read voltage on the bit line.

公开(公告)号：US11710733B2

公开(公告)日：2023-07-25

申请号：US16808336

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Lim ,  Bharani Chava ,  Foua Vang ,  Seung Hyuk Kang ,  Venugopal Boynapalli

IPC: H01L27/02 ,  H03K19/0185 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H03K19/018557

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2≤m m*P.

公开(公告)号：US11668735B2

公开(公告)日：2023-06-06

申请号：US16935092

申请日：2020-07-21

Applicant: QUALCOMM Incorporated

Inventor： Stefano Facchin ,  Baptiste Grave ,  Bharani Chava ,  David Jonathan Walshe

IPC: G02F1/1368 ,  G02F1/1362 ,  G01R19/165 ,  H01L23/528 ,  H01L27/092 ,  H01L29/24 ,  H01L29/786

CPC classification number: G01R19/16519 ,  G02F1/136286 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/24 ,  H01L29/7869 ,  G02F1/1368

Abstract: An IC is provided. The IC includes a power grid including Mx layer interconnects extending in a first direction on an Mx layer and Mx+1 layer interconnects extending in a second direction orthogonal to the first direction on an Mx+1 layer, where x>5. In addition, the IC includes a plurality of power switches. Further, the IC includes at least one sensing element located between the Mx layer and the Mx+1 layer and configured to measure a voltage drop to devices powered by the plurality of power switches. The one or more of the plurality of power switches may be located below the power grid. The power switches of the plurality of power switches may be adjacent in the first direction and in the second direction to each sensing element of the at least one sensing element.

公开(公告)号：US11552055B2

公开(公告)日：2023-01-10

申请号：US17100060

申请日：2020-11-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Bharani Chava

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking. To facilitate providing additional electrical routing paths for die-to-die interconnections between stacked IC dice in the IC package, a BS-BEOL metallization structure of a first die of the stacked dice of the IC package is stacked adjacent to a FS-BEOL metallization structure of a second die of the stacked IC dice. Electrical routing paths for die-to-die interconnections between the stacked IC dice are provided from the BS-BEOL metallization structure of the first die to the FS-BEOL metallization structure of the second die. It may be more feasible to form shorter electrical routing paths in the thinner BS-BEOL metallization structure than in a FS-BEM metallization structure for lower-resistance and/or lower-capacitance die-to-die interconnections for faster and/or compatible performance of semiconductor devices in the IC dice.

公开(公告)号：US11515289B2

公开(公告)日：2022-11-29

申请号：US17015308

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song ,  Abinash Roy ,  Jonghae Kim

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：US20220180910A1

公开(公告)日：2022-06-09

申请号：US17459186

申请日：2021-08-27

Applicant: QUALCOMM Incorporated

Inventor： Khaja Ahmad Shaik ,  Bharani Chava

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/419

Abstract: An exemplary memory bit cell circuit, including a bit line coupled to an SRAM bit cell circuit and an NVM bit cell circuit, with reduced area and reduced power consumption, included in a memory bit cell array circuit, is disclosed. The SRAM bit cell circuit includes cross-coupled true and complement inverters and a first access circuit coupled to the bit line. The NVM bit cell circuit includes an NVM device coupled to the bit line by a second access circuit and is coupled to the SRAM bit cell circuit. Data stored in the SRAM bit cell circuit and the NVM bit cell circuit are accessed based on voltages on the bit line. A true SRAM data is determined by an SRAM read voltage on the bit line, and an NVM data in the NVM bit cell circuit is determined by a first NVM read voltage on the bit line.

公开(公告)号：US11176991B1

公开(公告)日：2021-11-16

申请号：US17084779

申请日：2020-10-30

Applicant: QUALCOMM Incorporated

Inventor： Khaja Ahmad Shaik ,  Bharani Chava ,  Dawuth Shadulkhan Pathan

IPC: G11C7/00 ,  G11C11/4094 ,  G11C11/4096 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/404

Abstract: Low-power compute-in-memory (CIM) systems employing CIM circuits that include static random access memory (SRAM) bit cells circuits. The CIM circuits can be used for multiply-and-accumulate (MAC) operations. The CIM circuits can include five-transistor (5T) SRAM bit cells that each have a single bit line coupled to an access circuit for accessing the SRAM bit cell for read/write operations. The CIM circuit also includes a multiplication circuit (e.g., an exclusive OR (XOR)-based circuit) coupled to the SRAM bit cell. The CIM circuit is configured to perform multiplication of an input data value received by the multiplication circuit with a weight data value stored in the SRAM bit cell. The reduction of an access circuit in the 5T SRAM bit cell allows the pull-up voltage at a supply voltage rail coupled to the inverters of the 5T SRAM bit cell to be reduced to reduce standby power while providing storage stability.