公开(公告)号：US11430797B2

公开(公告)日：2022-08-30

申请号：US16917212

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Abinash Roy ,  Bharani Chava

IPC: H01L27/112 ,  H01L23/538 ,  H01L21/48

Abstract: Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor.

公开(公告)号：US11764186B2

公开(公告)日：2023-09-19

申请号：US17162621

申请日：2021-01-29

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Abinash Roy

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/58 ,  H03K17/687 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/58 ,  H01L24/16 ,  H03K17/6871 ,  H01L2224/16227

Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

公开(公告)号：US12057436B2

公开(公告)日：2024-08-06

申请号：US18365063

申请日：2023-08-03

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Abinash Roy

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H03K17/687

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/58 ,  H01L24/16 ,  H03K17/6871 ,  H01L2224/16227

Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The first power interconnect includes a first power plane. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The second power interconnect includes a second power plane. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

公开(公告)号：US11830819B2

公开(公告)日：2023-11-28

申请号：US17357811

申请日：2021-06-24

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Abinash Roy ,  Stanley Seungchul Song ,  Jonghae Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：US11249530B1

公开(公告)日：2022-02-15

申请号：US17105253

申请日：2020-11-25

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan Pal ,  Harshat Pant ,  Abinash Roy ,  Shih-Hsin Jason Hu ,  Keith Alan Bowman

IPC: G06F1/24 ,  G06F1/30 ,  G06F1/324 ,  G05F3/24 ,  G05F1/595

Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.

公开(公告)号：US10732697B2

公开(公告)日：2020-08-04

申请号：US15978902

申请日：2018-05-14

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra Srinivas ,  Abhijit Joshi ,  Bharat Kavala ,  Abinash Roy

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F1/30 ,  G06F1/26 ,  G06F1/28 ,  G06F1/18

Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for reducing latency in switching computing cores of a computing system between operating modes. Certain aspects provide a computing device including a plurality of computing cores, each configured to operate in any one of a plurality of operating modes. The computing device further includes a first voltage rail and a plurality of components, each associated with one of the computing cores. The computing device further includes a plurality of switches, each switch configured to selectively couple a corresponding one of the plurality of components to the first voltage rail. The computing device further includes a controller configured to determine a current operating mode of each of the plurality of computing cores and switch the plurality of switches at a first selected switching rate based on the determined current operating mode of each of the plurality of computing cores.

公开(公告)号：US11876085B2

公开(公告)日：2024-01-16

申请号：US17358838

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Abinash Roy ,  Lohith Kumar Vemula ,  Bharani Chava ,  Jonghae Kim

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64 ,  H01G4/232

CPC classification number: H01L25/16 ,  H01L21/4803 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/642 ,  H01G4/232

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.

公开(公告)号：US11515289B2

公开(公告)日：2022-11-29

申请号：US17015308

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song ,  Abinash Roy ,  Jonghae Kim

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：US10915157B2

公开(公告)日：2021-02-09

申请号：US16276532

申请日：2019-02-14

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan Pal ,  Jeffrey Gemar ,  Abinash Roy

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/3203

Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.