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    RADIO FREQUENCY OSCILLATOR WITH CERAMIC RESONATOR AND SURFACE-MOUNTED INTEGRATED CIRCUIT PACKAGE
    12.
    发明公开
    RADIO FREQUENCY OSCILLATOR WITH CERAMIC RESONATOR AND SURFACE-MOUNTED INTEGRATED CIRCUIT PACKAGE 审中-公开

    公开(公告)号：US20240322417A1

    公开(公告)日：2024-09-26

    申请号：US18189684

    申请日：2023-03-24

    Applicant: QUALCOMM Incorporated

    Inventor： Kai LIU ,  Jonghae KIM ,  Jui-Yi CHIU ,  Nosun PARK ,  Je-Hsiung LAN

    IPC: H01P7/10 ,  H01P11/00 ,  H03B5/12

    CPC classification number: H01P7/10 ,  H01P11/008 ,  H03B5/1206

    Abstract: In an aspect, an apparatus is disclosed that includes a surface-mounted integrated circuit package housing an active oscillator circuit; an integrated ceramic resonator formed from a ceramic substrate having an upper planar surface receiving the surface-mounted integrated circuit package, the integrated ceramic resonator including a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate, a conductive rod extending vertically into the ceramic cavity, wherein the conductive rod is isolated from contact with the conductive periphery of the ceramic cavity, a first conductive material extending vertically through the upper planar surface of the ceramic substrate for connecting the conductive periphery of the ceramic cavity to the surface-mounted integrated circuit package housing the active oscillator circuit; and a second conductive material extending through the upper planar surface of the ceramic substrate for connecting the conductive rod to the surface-mounted integrated circuit package.

    INTEGRATED DEVICES COMPRISING UNIFORM METAL LAYER THICKNESS ACROSS ONE OR MORE METAL LAYERS
    17.
    发明申请
    INTEGRATED DEVICES COMPRISING UNIFORM METAL LAYER THICKNESS ACROSS ONE OR MORE METAL LAYERS 有权

    公开(公告)号：US20210005545A1

    公开(公告)日：2021-01-07

    申请号：US16503237

    申请日：2019-07-03

    Applicant: QUALCOMM Incorporated

    Inventor： Kai LIU ,  Xia LI ,  Bin YANG

    IPC: H01L23/528 ,  H01L23/522

    Abstract: An integrated device that includes a substrate, a third plurality of interconnects formed on a third metal layer, a fourth plurality of interconnects formed on a fourth metal layer, at least one dielectric layer formed over the substrate. The third metal layer is located over the substrate. The third metal layer has a third pattern density. The third plurality of interconnects has a third thickness that is approximately the same for all interconnects of the third plurality of interconnects. The fourth metal layer is located over the third metal layer. The fourth metal layer has a fourth pattern density. The fourth pattern density is different than the third pattern density. The fourth plurality of interconnects has a fourth thickness that is approximately the same for all interconnects of the fourth plurality of interconnects.

    DEVICE COMPRISING STACKED THROUGH ENCAPSULATION VIA INTERCONNECTS
    18.
    发明申请
    DEVICE COMPRISING STACKED THROUGH ENCAPSULATION VIA INTERCONNECTS 有权

    公开(公告)号：US20250022858A1

    公开(公告)日：2025-01-16

    申请号：US18352976

    申请日：2023-07-14

    Applicant: QUALCOMM Incorporated

    Inventor： Kai LIU ,  Jui-Yi CHIU ,  Jonghae KIM ,  Je-Hsiung LAN ,  Nosun PARK

    IPC: H01L25/16 ,  H01L23/00 ,  H01L23/522

    Abstract: A device comprising (i) a first device portion comprising: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects located at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects and the second plurality of via interconnects are configured to operate as an inductor.

    COMPACT HYBRID ACOUSTIC WAVE FILTER STRUCTURE
    19.
    发明公开
    COMPACT HYBRID ACOUSTIC WAVE FILTER STRUCTURE 审中-公开

    公开(公告)号：US20240258995A1

    公开(公告)日：2024-08-01

    申请号：US18160917

    申请日：2023-01-27

    Applicant: QUALCOMM Incorporated

    Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Nosun PARK ,  Jui-Yi CHIU ,  Kai LIU

    IPC: H03H9/54 ,  H03H3/02 ,  H03H3/08 ,  H03H9/17 ,  H03H9/25 ,  H03H9/64

    CPC classification number: H03H9/542 ,  H01L28/40 ,  H03H3/02 ,  H03H3/08 ,  H03H9/171 ,  H03H9/25 ,  H03H9/64

    Abstract: A compact, hybrid, acoustic wave filter structure is disclosed. In an aspect an apparatus comprises a substrate; a first, multi-layer metallization structure disposed above the substrate; a plurality of pillar structures disposed above, and electrically coupled to, the first metallization structure; a second metallization structure disposed above, an electrically coupled to, the plurality of pillar structures. An acoustic unit (AU) is disposed between the first and second metallization structures and adjacent to at least one of the pillar structures. The AU comprises a surface acoustic wave or bulk acoustic wave acoustic resonator that is electrically coupled to a capacitor and an inductor. The capacitor comprises a metal-insulation-metal capacitor that is formed from a portion of the first metallization structure and optionally also from at least one pillar structure and a portion of the second metallization structure. The inductor is comprised of a second portion of the first metallization structure.

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