公开(公告)号：US09020084B2

公开(公告)日：2015-04-28

申请号：US13756491

申请日：2013-01-31

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Saravanan Marimuthu ,  Ohsang Kwon

IPC: H04L7/00 ,  H03K3/356

CPC classification number: H04L7/0045 ,  H03K3/356156 ,  H04L7/0037

Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

Abstract translation: 本文描述了用于解决同步器中的亚稳态的技术。 在一个实施例中，用于分解同步器中的亚稳态的电路包括耦合到同步器的节点的信号延迟电路，其中信号延迟电路被配置为延迟节点处的数据信号以产生延迟的数据信号，以及 耦合到所述信号延迟电路的传输电路，其中所述传输电路被配置为在从时钟信号的第一边缘延迟之后将所述延迟的数据信号耦合到所述节点。

公开(公告)号：US11437375B2

公开(公告)日：2022-09-06

申请号：US16744227

申请日：2020-01-16

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L23/535 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482 ,  H03K17/687 ,  H03K17/16 ,  H01L23/522

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US10580774B2

公开(公告)日：2020-03-03

申请号：US16057036

申请日：2018-08-07

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H03K17/16 ,  H03K17/687 ,  H01L23/482 ,  H01L27/02 ,  H01L23/535 ,  H01L23/522

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US09659936B2

公开(公告)日：2017-05-23

申请号：US13975074

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/482 ,  H01L27/02 ,  H03K17/16 ,  H03K17/687 ,  H01L23/522

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

公开(公告)号：US20160248414A1

公开(公告)日：2016-08-25

申请号：US14818114

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Dorav Kumar ,  Steven James Dillen ,  Ohsang Kwon ,  Javid Jaffari

IPC: H03K17/042 ,  H03K5/24

CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K5/26 ,  H03K19/0016

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

Abstract translation: 本文描述了为电路供电的系统和方法。 在一个实施例中，一种用于上电的方法包括将第一电源轨的电压与第二电源轨的电压进行比较，以及确定第一电源轨的电压是否在第二电源轨的电压的预定量内 至少基于该比较的预定时间段。 该方法还包括在确定第一电源轨的电压在第二电源轨的电压的预定量内至少在预定时间段内的情况下，启动耦合在第一和第二电源轨之间的多个开关的开关 时间。

公开(公告)号：US09318476B2

公开(公告)日：2016-04-19

申请号：US14195525

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Animesh Datta ,  Seid Hadi Rasouli

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2027/11861 ,  H01L2027/11866

Abstract: A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.

Abstract translation: 提供晶体管单元，其包括覆盖连续氧化物定义（OD）区域的虚拟栅极。 与虚设的第一侧相邻的OD区域的第一部分形成漏极。 单元包括局部互连结构，其将虚拟栅极和邻近伪栅极的第二相对侧的OD区域的一部分耦合到源极电压。

公开(公告)号：US20150070973A1

公开(公告)日：2015-03-12

申请号：US14023382

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Gaurav Bhargava ,  Ramaprasath Vilangudipitchai ,  Ohsang Kwon

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/10 ,  G11C29/022 ,  G11C29/32

Abstract: A latch-based array includes a plurality of columns and rows. Each column comprises a plurality of slave latches that all latch in parallel a master-latched data output from the column's master latch during normal operation. In a fault-testing mode of operation, one of the slaves in the column latches an inverted version of the master-latched data output while the remaining slave latches in the column latch the master-latched data output. In this fashion, the slave latches are decorrelated in a single write operation.

Abstract translation: 基于闩锁的阵列包括多个列和行。 每列包括多个从锁存器，它们在正常操作期间并行地从锁存器的主锁存器输出的主锁存数据并行锁存。 在故障测试操作模式下，列中的一个从站锁存主锁存数据输出的反向版本，而列中剩余的从锁存器锁存主锁存数据输出。 以这种方式，从锁存器在单次写入操作中被去相关。

公开(公告)号：US20140211893A1

公开(公告)日：2014-07-31

申请号：US13756491

申请日：2013-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Saravanan Marimuthu ,  Ohsang Kwon

IPC: H04L7/00

CPC classification number: H04L7/0045 ,  H03K3/356156 ,  H04L7/0037

Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

Abstract translation: 本文描述了用于解决同步器中的亚稳态的技术。 在一个实施例中，用于分解同步器中的亚稳态的电路包括耦合到同步器的节点的信号延迟电路，其中信号延迟电路被配置为延迟节点处的数据信号以产生延迟的数据信号，以及 耦合到所述信号延迟电路的传输电路，其中所述传输电路被配置为在从时钟信号的第一边缘延迟之后将所述延迟的数据信号耦合到所述节点。

公开(公告)号：US11508725B2

公开(公告)日：2022-11-22

申请号：US16777639

申请日：2020-01-30

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Michael Joseph Brunolli ,  Christine Sung-An Hau-Riege ,  Mickael Malabry ,  Sucheta Kumar Harish ,  Prathiba Balasubramanian ,  Kamesh Medisetti ,  Nikolay Bomshtein ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L23/482 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238 ,  H01L23/522 ,  H03K17/16 ,  H03K17/687

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

公开(公告)号：US10593700B2

公开(公告)日：2020-03-17

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L27/118 ,  H01L23/535 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.