公开(公告)号：US09455737B1

公开(公告)日：2016-09-27

申请号：US15049933

申请日：2016-02-22

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Changsok Han ,  Liang Dai ,  Seyed Arash Mirhaj ,  Ganesh Kiran

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M1/1023 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/47

Abstract: Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

Abstract translation: 本公开的某些方面提供了使用时间交织（TI）逐次逼近寄存器（SAR）模数转换器（ADC）的Δ-Σ调制器（DSM）。 例如，两个SAR ADC可以配置为交替采样和处理输入信号，并使用多余的环路延迟（ELD）为DSM提供反馈信号。 在其他方面，DSM可以使用两步SAR量化器来实现。 例如，第一SAR ADC可以采样输入信号以产生DSM的输出的最高有效位（MSB）部分，而第二SAR ADC可以随后从第一SAR ADC转换中采样残留，并产生最少 - DSM的输出的高位（LSB）部分。 利用这些技术，可以在高精度Δ-ΣADC中获得更高的带宽，而不使用提高的采样率。

公开(公告)号：US20150116020A1

公开(公告)日：2015-04-30

申请号：US14065854

申请日：2013-10-29

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Dinesh J. Alladi

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/356034 ,  H03K3/356069

Abstract: The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.

Abstract translation: 本公开包括用于锁存信号的电路和方法。 在一个实施例中，两个逆变器被背靠背配置以锁定信号。 每个逆变器包括配置在逆变器晶体管的控制端之间的电容器。 在一个实施例中，电路是比较器的一部分。 第一和第二电压被接收在差分晶体管的控制端上，并且差分输出信号耦合到两个背靠背的反相器。 在一个实施例中，电路被禁用，并且反相器中的晶体管的控制端子上的电压被设置为低于诸如电源的参考值，以增加电路的速度。

公开(公告)号：US08970304B2

公开(公告)日：2015-03-03

申请号：US13740013

申请日：2013-01-11

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee

IPC: H03F3/45

CPC classification number: H03F3/45188 ,  H03F2203/45301 ,  H03F2203/45311 ,  H03F2203/45371 ,  H03F2203/45661

Abstract: Exemplary embodiments are directed to systems, devices, and methods for enhancing a telescopic amplifier. An amplifier may include a differential pair of input transistors including at least one transistor configured to receive a first input and at least one other transistor configured to receive a second input. The amplifier may further include a cascode circuit including a first pair of transistors coupled to the at least one transistor of the differential pair to form a first plurality of current paths configured to generate a first output. The cascode circuit may also include a second pair of transistors coupled to the at least one other transistor of the differential pair to form a second plurality of currents paths configured to generate a second output.

Abstract translation: 示例性实施例涉及用于增强伸缩式放大器的系统，装置和方法。 放大器可以包括差分对的输入晶体管，其包括至少一个晶体管，其被配置为接收第一输入和至少一个被配置为接收第二输入的其他晶体管。 放大器还可以包括共源共栅电路，其包括耦合到差分对的至少一个晶体管的第一对晶体管，以形成被配置为产生第一输出的第一多个电流通路。 共源共同电路还可以包括耦合到差分对的至少一个其它晶体管的第二对晶体管，以形成被配置为产生第二输出的第二多个电流路径。

公开(公告)号：US20150022266A1

公开(公告)日：2015-01-22

申请号：US13944683

申请日：2013-07-17

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee

IPC: H03F3/45 ,  H03F3/19

CPC classification number: H03F3/45179 ,  H03F3/19 ,  H03F3/45192 ,  H03F2203/45364

Abstract: Exemplary embodiments are directed to systems, devices, and methods for enhancing an amplifier. An amplifier may include a first cascode circuit including a first transistor and a second transistor. The amplifier may include a second cascode circuit coupled to a differential output and including a first pair of transistors including a first transistor and a second transistor and a second pair of transistors including a third transistor and a fourth transistor. Further, the amplifier may include a differential input including a first transistor coupled to each of the first transistor of the first cascode circuit and the first and second transistors of the second cascode circuit, the differential input further including a second transistor coupled to each of the second transistor of the first cascode circuit and the third and fourth transistors of the second cascode circuit.

Abstract translation: 示例性实施例涉及用于增强放大器的系统，设备和方法。 放大器可以包括包括第一晶体管和第二晶体管的第一共源共栅电路。 放大器可以包括耦合到差分输出并包括包括第一晶体管和第二晶体管的第一对晶体管和包括第三晶体管和第四晶体管的第二对晶体管的第二共源共栅电路。 此外，放大器可以包括差分输入，该差分输入包括耦合到第一共源共栅电路的第一晶体管中的每一个的第一晶体管和第二共源共栅电路的第一和第二晶体管，差分输入还包括耦合到 第二共源共栅电路的第二晶体管和第二共源共栅电路的第三和第四晶体管。