公开(公告)号：US20160087607A1

公开(公告)日：2016-03-24

申请号：US14495744

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Wei Huang ,  Yuhua Guo

IPC: H03K3/011 ,  H03K5/24

CPC classification number: H03K5/2481 ,  H03K3/023

Abstract: Pumping current into a regeneration latch of a comparator, including: a first transistor configured to receive a first constant current from a first constant current source; a first current mirror coupled to the first transistor and configured to provide a first bias current, wherein the first transistor substantially mirrors the first constant current into the first bias current in the first current mirror; a second transistor configured to receive a second constant current from a second constant current source; a second current mirror coupled to the second transistor and configured to provide a second bias current, wherein the second transistor substantially mirrors the second constant current into the second bias current in the second current mirror; and a third transistor configured to combine the first bias current and the second bias current, wherein the third transistor pumps the combined bias current into the regeneration latch.

Abstract translation: 将电流泵送到比较器的再生锁存器中，包括：第一晶体管，被配置为从第一恒定电流源接收第一恒定电流; 耦合到所述第一晶体管并被配置为提供第一偏置电流的第一电流镜，其中所述第一晶体管基本上将所述第一恒定电流反射到所述第一电流镜中的所述第一偏置电流; 第二晶体管，被配置为从第二恒定电流源接收第二恒定电流; 耦合到所述第二晶体管并被配置为提供第二偏置电流的第二电流镜，其中所述第二晶体管基本上将所述第二恒定电流反射到所述第二电流镜中的所述第二偏置电流; 以及第三晶体管，被配置为组合所述第一偏置电流和所述第二偏置电流，其中所述第三晶体管将所述组合的偏置电流泵送到所述再生锁存器中。

公开(公告)号：US09083296B2

公开(公告)日：2015-07-14

申请号：US13944683

申请日：2013-07-17

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee

IPC: H03F3/45 ,  H03F3/19

CPC classification number: H03F3/45179 ,  H03F3/19 ,  H03F3/45192 ,  H03F2203/45364

Abstract: Exemplary embodiments are directed to systems, devices, and methods for enhancing an amplifier. An amplifier may include a first cascode circuit including a first transistor and a second transistor. The amplifier may include a second cascode circuit coupled to a differential output and including a first pair of transistors including a first transistor and a second transistor and a second pair of transistors including a third transistor and a fourth transistor. Further, the amplifier may include a differential input including a first transistor coupled to each of the first transistor of the first cascode circuit and the first and second transistors of the second cascode circuit, the differential input further including a second transistor coupled to each of the second transistor of the first cascode circuit and the third and fourth transistors of the second cascode circuit.

Abstract translation: 示例性实施例涉及用于增强放大器的系统，设备和方法。 放大器可以包括包括第一晶体管和第二晶体管的第一共源共栅电路。 放大器可以包括耦合到差分输出并包括包括第一晶体管和第二晶体管的第一对晶体管和包括第三晶体管和第四晶体管的第二对晶体管的第二共源共栅电路。 此外，放大器可以包括差分输入，该差分输入包括耦合到第一共源共栅电路的第一晶体管中的每一个的第一晶体管和第二共源共栅电路的第一和第二晶体管，差分输入还包括耦合到 第二共源共栅电路的第二晶体管和第二共源共栅电路的第三和第四晶体管。

公开(公告)号：US20140253210A1

公开(公告)日：2014-09-11

申请号：US13787590

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Omid Rajaee ,  Wei Zheng ,  Dinesh J. Alladi ,  Yuhua Guo

IPC: H03K5/156 ,  H03K3/012 ,  H03L5/00

CPC classification number: H03K5/1565 ,  H03K3/012 ,  H03K3/35613 ,  H03K19/01714 ,  H03K19/018521 ,  H03L5/00

Abstract: Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.

Abstract translation: 本公开的某些方面提供了采用低等待时间交流耦合升压电路的电压电平移位电路，以及包括这种电平转换电路的其它电路和装置。 与常规电平转换器相比，这种电平移位电路提供显着更低的等待时间（例如，延迟减少至少两倍）。 与模拟角相比，提供一致的延迟，与此相比，电平移位电路与常规电平转换器相比，也提供了显着更低的功耗和减少的占空比失真。

公开(公告)号：US10044365B1

公开(公告)日：2018-08-07

申请号：US15843718

申请日：2017-12-15

Applicant: QUALCOMM Incorporated

Inventor： Liang Dai ,  Kentaro Yamamoto ,  Omid Rajaee ,  Li Lu ,  Dinesh Alladi ,  Changsok Han

IPC: H03M1/50 ,  H03L7/081 ,  H04W84/04 ,  H03M3/00

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for analog-to-digital conversion using a time-to-digital converter (TDC). For example, certain aspects provide a quantizer using a TDC. The quantizer may include at least one first capacitive element and a set of switches configured to selectively couple a first terminal and a second terminal of the at least one first capacitive element to at least one input voltage source. The TDC may also include a reference voltage source, at least one switch coupled between the second terminal of the at least one first capacitive element and an output of the reference voltage source, a current source selectively coupled to the first terminal of the at least one first capacitive element, and a voltage sense circuit coupled to the first terminal of the at least one first capacitive element.

公开(公告)号：US09425818B1

公开(公告)日：2016-08-23

申请号：US14724555

申请日：2015-05-28

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Dinesh Jagannath Alladi ,  Liang Dai

IPC: H03M3/00

CPC classification number: H03M3/426 ,  H03M1/466 ,  H03M3/32 ,  H03M3/436

Abstract: An analog-to-digital converter includes: a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; a noise shaping module configured to compare the first input signal to the second input signal received, and to output a digital output signal and a residue signal in a first phase of a noise shaping operation; and a storage module configured to store the residue signal during the first phase of the noise shaping operation, the storage module configured to receive an analog input signal and remove the residue signal from the analog input signal in a second phase of the noise shaping operation to output a new first input signal to the noise shaping module.

Abstract translation: 模数转换器包括：第一输入端，用于接收第一输入信号; 第二输入端子，用于接收第二输入信号; 噪声整形模块，其被配置为将所述第一输入信号与所接收的所述第二输入信号进行比较，并且在噪声整形操作的第一阶段中输出数字输出信号和残留信号; 以及存储模块，被配置为在所述噪声整形操作的第一阶段期间存储所述残留信号，所述存储模块被配置为在所述噪声整形操作的第二阶段中接收模拟输入信号并从所述模拟输入信号中去除所述残留信号， 向噪声整形模块输出新的第一输入信号。

公开(公告)号：US09306553B2

公开(公告)日：2016-04-05

申请号：US13787590

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Wei Zheng ,  Dinesh Jagannath Alladi ,  Yuhua Guo

IPC: H03L5/00 ,  H03K5/156 ,  H03K3/012 ,  H03K3/356 ,  H03K19/017 ,  H03K19/0185

CPC classification number: H03K5/1565 ,  H03K3/012 ,  H03K3/35613 ,  H03K19/01714 ,  H03K19/018521 ,  H03L5/00

Abstract: Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.

Abstract translation: 本公开的某些方面提供了采用低等待时间交流耦合升压电路的电压电平移位电路，以及包括这种电平转换电路的其它电路和装置。 与常规电平转换器相比，这种电平移位电路提供显着更低的等待时间（例如，延迟减少至少两倍）。 与模拟角相比，提供一致的延迟，与此相比，电平移位电路与常规电平转换器相比，也提供了显着更低的功耗和减少的占空比失真。

公开(公告)号：US10277241B1

公开(公告)日：2019-04-30

申请号：US15961631

申请日：2018-04-24

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Elias Dagher ,  Yan Wang ,  Dinesh Jagannath Alladi

IPC: H03M1/18 ,  H03M1/66 ,  H03M3/00

Abstract: A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.

公开(公告)号：US09608658B1

公开(公告)日：2017-03-28

申请号：US15014865

申请日：2016-02-03

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Liang Dai ,  Ganesh Kiran

IPC: H03M1/12 ,  H03M1/38 ,  H03M1/10

CPC classification number: H03M1/38 ,  H03M1/1009 ,  H03M1/1014 ,  H03M1/188

Abstract: Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

公开(公告)号：US09197198B2

公开(公告)日：2015-11-24

申请号：US14065854

申请日：2013-10-29

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Dinesh J Alladi

IPC: H03K5/22 ,  H03K3/037 ,  H03K3/356

CPC classification number: H03K3/0375 ,  H03K3/356034 ,  H03K3/356069

Abstract: The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.

Abstract translation: 本公开包括用于锁存信号的电路和方法。 在一个实施例中，两个逆变器被背靠背配置以锁定信号。 每个逆变器包括配置在逆变器晶体管的控制端之间的电容器。 在一个实施例中，电路是比较器的一部分。 第一和第二电压被接收在差分晶体管的控制端上，并且差分输出信号耦合到两个背靠背的反相器。 在一个实施例中，电路被禁用，并且反相器中的晶体管的控制端子上的电压被设置为低于诸如电源的参考值，以增加电路的速度。

公开(公告)号：US20140197888A1

公开(公告)日：2014-07-17

申请号：US13740013

申请日：2013-01-11

Applicant: QUALCOMM INCORPORATED

Inventor： Omid Rajaee

IPC: H03F3/45

CPC classification number: H03F3/45188 ,  H03F2203/45301 ,  H03F2203/45311 ,  H03F2203/45371 ,  H03F2203/45661

Abstract: Exemplary embodiments are directed to systems, devices, and methods for enhancing a telescopic amplifier. An amplifier may include a differential pair of input transistors including at least one transistor configured to receive a first input and at least one other transistor configured to receive a second input. The amplifier may further include a cascode circuit including a first pair of transistors coupled to the at least one transistor of the differential pair to form a first plurality of current paths configured to generate a first output. The cascode circuit may also include a second pair of transistors coupled to the at least one other transistor of the differential pair to form a second plurality of currents paths configured to generate a second output.

Abstract translation: 示例性实施例涉及用于增强伸缩式放大器的系统，装置和方法。 放大器可以包括差分对的输入晶体管，其包括至少一个晶体管，其被配置为接收第一输入和至少一个被配置为接收第二输入的其他晶体管。 放大器还可以包括共源共栅电路，其包括耦合到差分对的至少一个晶体管的第一对晶体管，以形成被配置为产生第一输出的第一多个电流通路。 共源共同电路还可以包括耦合到差分对的至少一个其它晶体管的第二对晶体管，以形成被配置为产生第二输出的第二多个电流路径。