公开(公告)号：US20220368299A1

公开(公告)日：2022-11-17

申请号：US17320077

申请日：2021-05-13

Applicant: Qualcomm Incorporated

Inventor： Kentaro Yamamoto ,  Aram Akhavan ,  Ganesh Kiran ,  Lei Sun ,  Elias Dagher ,  Dinesh Jagannath Alladi

IPC: H03G3/30 ,  H03M1/12 ,  H03F3/19 ,  H03F3/21

Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

公开(公告)号：US10594308B1

公开(公告)日：2020-03-17

申请号：US16236721

申请日：2018-12-31

Applicant: QUALCOMM Incorporated

Inventor： Lei Sun ,  Ganesh Kiran ,  Seyed Arash Mirhaj ,  Dinesh Jagannath Alladi

IPC: H03M1/10 ,  H03K5/24 ,  H03M1/46

Abstract: Methods and apparatus for digitally controlling a common-mode voltage of a comparator. An example comparator circuit generally includes a first comparator and a sensing circuit configured to digitally track a common-mode voltage of the first comparator. The comparator circuit may further include a first capacitive array having a common terminal coupled to a first input of the first comparator and selectively coupled to an input of the sensing circuit. The comparator circuit may further include a second capacitive array having a common terminal coupled to a second input of the first comparator and selectively coupled to the input of the sensing circuit.

公开(公告)号：US20160181983A1

公开(公告)日：2016-06-23

申请号：US14577950

申请日：2014-12-19

Applicant: QUALCOMM Incorporated

Inventor： Ganesh Kiran

IPC: H03F1/02 ,  H03F1/22 ,  H03F3/45

CPC classification number: H03F1/0205 ,  H03F1/223 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45179 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/456 ,  H03F2203/45288 ,  H03F2203/45364 ,  H03F2203/45644 ,  H03F2203/45651 ,  H03H11/0427 ,  H03H19/004

Abstract: A low power operational transconductance amplifier is disclosed. In an exemplary embodiment, an apparatus includes a transconductance stage configured to convert a first input voltage signal to first and second current signals and to convert a second input voltage signal to third and fourth current signals. The apparatus also includes a current amplification stage configured to amplify the second current signal to generate a first amplified current signal and to amplify the fourth current signal to generate a second amplified current signal. The apparatus also includes a current summation stage configured to sum together the third current signal and the first amplified current signal to generate a first output voltage signal, and to sum together the first current signal and the second amplified current signal to generate a second output voltage signal.

Abstract translation: 公开了一种低功率运算跨导放大器。 在示例性实施例中，一种装置包括跨导级，其经配置以将第一输入电压信号转换为第一和第二电流信号，并将第二输入电压信号转换为第三和第四电流信号。 该装置还包括电流放大级，配置为放大第二电流信号以产生第一放大电流信号并放大第四电流信号以产生第二放大电流信号。 该装置还包括电流求和级，其被配置为将第三电流信号和第一放大电流信号相加在一起以产生第一输出电压信号，并且将第一电流信号和第二放大电流信号相加在一起以产生第二输出电压 信号。

公开(公告)号：US09608658B1

公开(公告)日：2017-03-28

申请号：US15014865

申请日：2016-02-03

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Liang Dai ,  Ganesh Kiran

IPC: H03M1/12 ,  H03M1/38 ,  H03M1/10

CPC classification number: H03M1/38 ,  H03M1/1009 ,  H03M1/1014 ,  H03M1/188

Abstract: Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

公开(公告)号：US11569837B1

公开(公告)日：2023-01-31

申请号：US17403683

申请日：2021-08-16

Applicant: QUALCOMM Incorporated

Inventor： Aram Akhavan ,  Kentaro Yamamoto ,  Lei Sun ,  Ganesh Kiran

IPC: H03M1/12 ,  H03M1/16 ,  H03F3/45

Abstract: Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

公开(公告)号：US10680596B1

公开(公告)日：2020-06-09

申请号：US16399630

申请日：2019-04-30

Applicant: QUALCOMM Incorporated

Inventor： Lei Sun ,  Ganesh Kiran ,  Seyed Arash Mirhaj

IPC: H02M1/08 ,  H03K17/041 ,  H04M1/02

Abstract: A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped switch transistor so that an input voltage signal may conduct through the bootstrapped switch transistor to charge a sampling node.

公开(公告)号：US09455737B1

公开(公告)日：2016-09-27

申请号：US15049933

申请日：2016-02-22

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Changsok Han ,  Liang Dai ,  Seyed Arash Mirhaj ,  Ganesh Kiran

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M1/1023 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/47

Abstract: Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

Abstract translation: 本公开的某些方面提供了使用时间交织（TI）逐次逼近寄存器（SAR）模数转换器（ADC）的Δ-Σ调制器（DSM）。 例如，两个SAR ADC可以配置为交替采样和处理输入信号，并使用多余的环路延迟（ELD）为DSM提供反馈信号。 在其他方面，DSM可以使用两步SAR量化器来实现。 例如，第一SAR ADC可以采样输入信号以产生DSM的输出的最高有效位（MSB）部分，而第二SAR ADC可以随后从第一SAR ADC转换中采样残留，并产生最少 - DSM的输出的高位（LSB）部分。 利用这些技术，可以在高精度Δ-ΣADC中获得更高的带宽，而不使用提高的采样率。

公开(公告)号：US11870404B2

公开(公告)日：2024-01-09

申请号：US17320077

申请日：2021-05-13

Applicant: Qualcomm Incorporated

Inventor： Kentaro Yamamoto ,  Aram Akhavan ,  Ganesh Kiran ,  Lei Sun ,  Elias Dagher ,  Dinesh Jagannath Alladi

IPC: H03G3/10 ,  H03G3/30 ,  H03F3/19 ,  H03F3/21 ,  H03M1/12

CPC classification number: H03G3/3036 ,  H03F3/19 ,  H03F3/21 ,  H03M1/124 ,  H03F2200/453

Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

公开(公告)号：US20200212904A1

公开(公告)日：2020-07-02

申请号：US16399630

申请日：2019-04-30

Applicant: QUALCOMM Incorporated

Inventor： Lei Sun ,  Ganesh Kiran ,  Seyed Arash Mirhaj

IPC: H03K17/041

Abstract: A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped switch transistor so that an input voltage signal may conduct through the bootstrapped switch transistor to charge a sampling node.