公开(公告)号：US20210384310A1

公开(公告)日：2021-12-09

申请号：US16893993

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234

Abstract: Gate-all-around (GAA) transistors with an additional bottom channel for reduced parasitic capacitance and methods of fabricating the same include one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire or nanoslab semiconductors, are surrounded by gate material. The GAA transistor further includes an additional semiconductor channel between a bottom section of a gate material and a silicon on insulator (SOI) substrate in a GAA transistor. This additional channel, sometimes referred to as a bottom channel, may be thinner than other channels in the GAA transistor and may have a thickness less than its length.

公开(公告)号：US11189617B2

公开(公告)日：2021-11-30

申请号：US16774278

申请日：2020-01-28

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Ye Lu ,  Junjing Bao ,  Chenjie Tang

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10 ,  H01L27/092 ,  H01L29/49 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/311 ,  H01L21/306

Abstract: Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure.

公开(公告)号：US11502079B2

公开(公告)日：2022-11-15

申请号：US16817446

申请日：2020-03-12

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Hyunwoo Park ,  Peijie Feng

IPC: H01L27/092 ,  H01L29/06

Abstract: An integrated device that includes a substrate, a first transistor, and a second transistor. The second transistor is configured to be coupled to the first transistor. The first transistor is configured to operate as a N-type channel metal oxide semiconductor transistor (NMOS) transistor. The first transistor includes a dielectric layer disposed over the substrate; a first source disposed over the dielectric layer; a first drain disposed over the dielectric layer; a first plurality of channels coupled to the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor is configured to operate as a P-type channel metal oxide semiconductor transistor (PMOS). The second transistor includes the dielectric layer; a second source disposed over the dielectric layer; a second drain disposed over the dielectric layer; a second plurality of channels coupled to the second source and the second drain; and a second gate.

公开(公告)号：US20220037493A1

公开(公告)日：2022-02-03

申请号：US16944624

申请日：2020-07-31

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/167

Abstract: Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same provide a GAA transistor that includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate and the source and drain regions, a filler material is provided adjacent the bottom gate, and the source and drain regions are grown on top of the filler material. In this fashion, the bottom gate does not abut the source region or the drain region, reducing geometries which would contribute to parasitic capacitance.

公开(公告)号：US10763364B1

公开(公告)日：2020-09-01

申请号：US16895909

申请日：2020-06-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US20170207313A1

公开(公告)日：2017-07-20

申请号：US15213879

申请日：2016-07-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  Peijie Feng ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure employing recessed conductive structures for conductively coupling nanowire structures are disclosed. Conductive structures are disposed between adjacent nanowire structures to conductively couple nanowire structures. Providing conductive structures in the nanowire channel structure increases the average cross-sectional area of nanowire structures, as compared to a similar nanowire channel structure not employing conductive structures, thus increasing effective channel width and drive strength for a given channel structure height. The precision of a gate material filling process is also eased, because gate material does not have to be disposed in areas between adjacent nanowire structures occupied by conductive structures. The conductive structure width can also be recessed with regard to width of nanowire structures in the nanowire channel structure to allow for a thicker metal gate to lower the gate resistance, while providing excellent electrostatic gate control of the channel.

公开(公告)号：US20240371924A1

公开(公告)日：2024-11-07

申请号：US18313060

申请日：2023-05-05

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Yan Sun ,  Shreesh Narasimha

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Enhanced-shaped extension region for gate-all-around (GAA) field-effect transistor (FET) devices and related fabrication methods are disclosed. The GAA FET device includes an extension region of semiconductor material coupled from the respective channel to the source/drain region to facilitate forming a conductive channel between the source and the drain regions when the GAA FET device is activated. The area of the extension region between the source/drain regions and the channel forms a series resistance between source/drain regions and the channel. To reduce channel parasitic resistance, the extension region of the GAA FET device has an enhanced extension portion that has an extended height orthogonal to the channel direction. The extension region with its enhanced extension portion has reduced resistance as compared to an extension region not containing the enhanced extension portion, thus reducing channel parasitic resistance of the GAA FET device for improved performance.

公开(公告)号：US11545555B2

公开(公告)日：2023-01-03

申请号：US16944624

申请日：2020-07-31

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L29/167 ,  H01L29/78 ,  H01L29/06

Abstract: Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same provide a GAA transistor that includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate and the source and drain regions, a filler material is provided adjacent the bottom gate, and the source and drain regions are grown on top of the filler material. In this fashion, the bottom gate does not abut the source region or the drain region, reducing geometries which would contribute to parasitic capacitance.

公开(公告)号：US11411092B2

公开(公告)日：2022-08-09

申请号：US16868376

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Ye Lu ,  Peijie Feng ,  Chenjie Tang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L21/02 ,  H01L21/764

Abstract: An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

公开(公告)号：US20210320197A1

公开(公告)日：2021-10-14

申请号：US16844479

申请日：2020-04-09

Applicant: QUALCOMM Incorporated

Inventor： Chenjie Tang ,  Ye Lu ,  Peijie Feng ,  Junjing Bao

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L21/02

Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.