公开(公告)号：US20070055953A1

公开(公告)日：2007-03-08

申请号：US11510415

申请日：2006-08-25

申请人： Weiping Fang ,  Huijuan Zhang ,  Yibing Wang ,  Zongwu Tang

发明人： Weiping Fang ,  Huijuan Zhang ,  Yibing Wang ,  Zongwu Tang

IPC分类号： G06F17/50 ,  G06K9/00

CPC分类号： G03F1/36 ,  G03F1/68

摘要： A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements. The system then computes environments for cell placements based on the skeleton. Next, the system generates templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement. The system then generates the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.

摘要翻译： 根据预期设计验证模拟晶片图像的系统。 在运行过程中，系统接收到一个设计。 接下来，系统从设计生成骨架，其中骨架指定单元格展示位置的单元格展示位置和相关联的边界框，但不包括单元格展示位置的几何。 然后系统基于骨架计算单元格展示位置的环境。 接下来，系统生成单元格展示位置的模板，其中单元格展示位置的模板指定单元格展示位置和单元格展示位置周围的环境。 然后，系统通过对与唯一模板相关联的单元格展示执行基于模型的模拟来生成模拟的晶片图像。

公开(公告)号：US08037428B2

公开(公告)日：2011-10-11

申请号：US12129617

申请日：2008-05-29

申请人： Yang-Shan Tong ,  Daniel Zhang ,  Linni Wei ,  Alex Miloslavsky ,  Wei-Chih Tseng ,  Zongwu Tang

发明人： Yang-Shan Tong ,  Daniel Zhang ,  Linni Wei ,  Alex Miloslavsky ,  Wei-Chih Tseng ,  Zongwu Tang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： One embodiment of the present invention provides a system that verifies an integrated circuit (IC) chip layout. During operation, the system receives a layout of an IC chip after the layout has gone through a place-and-route operation. Next, the system performs a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot. Next, for each detected lithography hotspot, the system compares the associated local routing pattern against a hotspot database to determine if the local routing pattern matches an entry in the hotspot database, which stores a set of known hotspot configurations. If so, the system corrects the lithography hotspot using correction guidance information associated with the hotspot configuration stored in the hotspot database. Otherwise, the system corrects the lithography hotspot by performing a local rip-up and reroute on the local routing pattern, iteratively, until achieving convergence or given number of iterations.

摘要翻译： 本发明的一个实施例提供一种验证集成电路（IC）芯片布局的系统。 在操作过程中，系统在布局经过布线操作后接收IC芯片的布局。 接下来，系统在布局上执行光刻柔性检查（LCC）操作以检测布局内的光刻热点，其中每个光刻热点与光刻热点周围的局部布线图案相关联。 接下来，对于每个检测到的光刻热点，系统将相关联的本地路由模式与热点数据库进行比较，以确定本地路由模式是否匹配热点数据库中存储一组已知热点配置的条目。 如果是，则系统使用与存储在热点数据库中的热点配置相关联的校正指导信息来校正光刻热点。 否则，系统通过对本地路由模式执行局部的rip-up和重新路由来迭代地校正光刻热点，直到达到收敛或给定的迭代次数。

公开(公告)号：US20090268958A1

公开(公告)日：2009-10-29

申请号：US12275887

申请日：2008-11-21

申请人： Kent Y. Kwang ,  Daniel Zhang ,  Zongwu Tang ,  Subarnarekha Sinha

发明人： Kent Y. Kwang ,  Daniel Zhang ,  Zongwu Tang ,  Subarnarekha Sinha

IPC分类号： G06K9/00

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： One embodiment of the present invention provides a system that automatically processes manufacturing hotspot information. During operation, the system receives a pattern clip associated with a manufacturing hotspot in a layout, wherein the pattern clip comprises a set of polygons in proximity to the manufacturing hotspot's location. Next, the system determines if the pattern clip matches a known manufacturing hotspot configuration. If the pattern clip does not match a known manufacturing hotspot configuration, the system then performs a perturbation process on the pattern clip to determine a set of correction recommendations to eliminate the manufacturing hotspot. By performing the perturbation process, the system additionally determines ranges of perturbation to the set of polygons wherein the perturbed pattern clip does not eliminate the manufacturing hotspot. Subsequently, the system stores the set of correction recommendations and the ranges of perturbation into a manufacturing hotspot database.

摘要翻译： 本发明的一个实施例提供一种自动处理制造热点信息的系统。 在操作期间，系统接收与布局中的制造热点相关联的图案剪辑，其中图案剪辑包括靠近制造热点位置的一组多边形。 接下来，系统确定模式剪辑是否匹配已知的制造热点配置。 如果图案剪辑与已知的制造热点配置不匹配，则系统然后对图案剪辑执行扰动处理，以确定一组校正建议以消除制造热点。 通过执行扰动过程，系统另外确定对该组多边形的扰动范围，其中扰动图案片不消除制造热点。 随后，系统将修正建议的集合和扰动范围存储到制造热点数据库中。

公开(公告)号：US07496884B2

公开(公告)日：2009-02-24

申请号：US11510415

申请日：2006-08-25

申请人： Weiping Fang ,  Huijuan Zhang ,  Yibing Wang ,  Zongwu Tang

发明人： Weiping Fang ,  Huijuan Zhang ,  Yibing Wang ,  Zongwu Tang

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/68

摘要： A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements. The system then computes environments for cell placements based on the skeleton. Next, the system generates templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement. The system then generates the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.

摘要翻译： 根据预期设计验证模拟晶片图像的系统。 在运行过程中，系统接收到一个设计。 接下来，系统从设计生成骨架，其中骨架指定单元格展示位置的单元格展示位置和相关联的边界框，但不包括单元格展示位置的几何。 然后系统基于骨架计算单元格展示位置的环境。 接下来，系统生成单元格展示位置的模板，其中单元格展示位置的模板指定单元格展示位置和单元格展示位置周围的环境。 然后，系统通过对与唯一模板相关联的单元格展示执行基于模型的模拟来生成模拟的晶片图像。