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公开(公告)号：US09042438B2
公开(公告)日：2015-05-26
申请号：US14572590
申请日：2014-12-16
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
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公开(公告)号：US09419827B2
公开(公告)日：2016-08-16
申请号：US14865825
申请日：2015-09-25
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
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公开(公告)号：US20150312062A1
公开(公告)日：2015-10-29
申请号：US14687721
申请日：2015-04-15
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
Abstract translation: 多相部分响应接收器通过在至少两个时钟相位中选择的一个采样PrDFE输出值来支持各种输入数据速率。 该接收机包括一个校准电路，该校准电路对电路中的关键数据路径进行定时分析，然后使用该分析来选择用于锁存输出值的特定时钟相位。 这些技术允许来自部分响应接收机的每个相位的多路复用器输出直接驱动用于随后阶段的多路复用器的选择，即通过避免各个多路复用器输出中的不稳定性或不确定性的区域。
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公开(公告)号：US11669124B2
公开(公告)日：2023-06-06
申请号：US17715869
申请日：2022-04-07
Applicant: Rambus Inc.
Inventor： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
CPC classification number: G06F1/08 , G06F1/12 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , H04L7/0008 , H04L7/0033 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/14 , H04L7/0004
Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
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公开(公告)号：US20170344050A1
公开(公告)日：2017-11-30
申请号：US15616795
申请日：2017-06-07
Applicant: Rambus Inc.
Inventor： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
CPC classification number: G06F1/08 , G06F1/12 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , H04L7/0004 , H04L7/0008 , H04L7/0033 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/14
Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
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Patent Agency Ranking
公开(公告)号：US09768986B2
公开(公告)日：2017-09-19
申请号：US15209375
申请日：2016-07-13
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
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公开(公告)号：US20170070369A1
公开(公告)日：2017-03-09
申请号：US15209375
申请日：2016-07-13
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
Abstract translation: 多相部分响应接收器通过在至少两个时钟相位中选择的一个采样PrDFE输出值来支持各种输入数据速率。 该接收机包括一个校准电路，该校准电路对电路中的关键数据路径进行定时分析，然后使用该分析来选择用于锁存输出值的特定时钟相位。 这些技术允许来自部分响应接收机的每个相位的多路复用器输出直接驱动用于随后阶段的多路复用器的选择，即通过避免各个多路复用器输出中的不稳定性或不确定性的区域。
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公开(公告)号：US20160087818A1
公开(公告)日：2016-03-24
申请号：US14865825
申请日：2015-09-25
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
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公开(公告)号：US09124390B2
公开(公告)日：2015-09-01
申请号：US13949101
申请日：2013-07-23
Applicant: RAMBUS INC.
Inventor： Scott C Best , Abhijit M Abhyankar , Kun-Yung Chang , Frank Lambrecht
CPC classification number: G06F1/08 , G06F1/12 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , H04L7/0004 , H04L7/0008 , H04L7/0033 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/14
Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.
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公开(公告)号：US09083280B2
公开(公告)日：2015-07-14
申请号：US14452187
申请日：2014-08-05
Applicant: Rambus Inc.
Inventor： Brian Leibowitz , Hae-Chang Lee , Farshid Aryanfar , Kun-Yung Chang , Jie Shen
CPC classification number: H03D13/00 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/085
Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.
Abstract translation: 相位检测电路可以包括两个相位检测器，每个相位检测器响应于相位对齐的输入信号而产生非零输出。 输入信号基于两个周期信号。 相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。 或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。 相位比较信号响应于相位检测器的相位输入信号具有非零值。 输入信号基于周期信号。 输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。
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