公开(公告)号：US20130256783A1

公开(公告)日：2013-10-03

申请号：US13766148

申请日：2013-02-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki KATOU ,  Taro MORIYA ,  Hiroyoshi KUDOU ,  Satoshi UCHIYA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L27/0629 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7827

Abstract: A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n+-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n+-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n+-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n+-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.

Abstract translation: 沟槽栅型MISFET和二极管形成在半导体衬底中。 第一和第二沟槽形成在半导体衬底中。 栅电极通过栅极绝缘膜形成在第一沟槽中。 虚拟栅电极通过虚拟栅极绝缘膜形成在第二沟槽中。 阴极n +型半导体区域和阳极p型半导体区域形成在半导体衬底中，并且第二沟槽形成为在平面图中包围n +型半导体区域。 阳极p型半导体区域的一部分直接形成在n +型半导体区域正下方，从而在阳极p型半导体区域和n +型半导体区域的部分之间形成PN结。 从而形成二极管。 虚拟栅电极电耦合到阳极和阴极之一。

公开(公告)号：US20240162222A1

公开(公告)日：2024-05-16

申请号：US18509870

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L28/20 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813

Abstract: Reliability of a semiconductor device is improved and reduction in yield is reduced. In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. In the semiconductor substrate SUB, a body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. The source region NS, the n-type source region, the n-type drain region, the p-type source region and the p-type drain region are subjected to heat treatment. After heat treatment, a p-type column region PC is formed in the semiconductor substrate SUB located below the body region PB.

公开(公告)号：US20240162143A1

公开(公告)日：2024-05-16

申请号：US18509874

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76885 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a semiconductor substrate SUB, a trench TR is formed.
A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. A body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. An interlayer insulating film IL1 is formed on the upper surface of semiconductor substrate SUB. In the interlayer insulating film IL1, a hole CH1 is formed in the source region NS and in the body region PB. Holes CH3 are formed in the interlayer insulating film IL1 so as to reach the n-type source region, the n-type drain region, the p-type source region and the p-type drain region.

公开(公告)号：US20180366575A1

公开(公告)日：2018-12-20

申请号：US15956611

申请日：2018-04-18

Applicant: Renesas Electronics Corporation

Inventor： Hiroyoshi KUDOU ,  Satoru TOKUDA ,  Satoshi UCHIYA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L23/4824 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7803

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; a first wiring and a second wiring disposed on the first surface; a first conductive film electrically connected to the first wiring; and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The drift region is disposed so as to surround the body region in a plan view. The first wiring has a first portion disposed so as to extend across a boundary between the drift region and the body region in a plan view, and electrically connected to the drift region. The second wiring is electrically connected to the source region. The first conductive film is insulated from and faces the second wiring.

公开(公告)号：US20150228737A1

公开(公告)日：2015-08-13

申请号：US14688072

申请日：2015-04-16

Applicant: Renesas Electronics Corporation

Inventor： Hiroaki KATOU ,  Taro MORIYA ,  Satoshi UCHIYA ,  Hiroyoshi KUDOU

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view.

Abstract translation: 半导体器件包括设置在第一导电类型的漏极区域上的第二导电类型的基极区域，设置成覆盖基极区域的外周端并且具有较低的杂质浓度的第二导电类型的外围阱区域 与基极区相比埋入半导体衬底中的不与外围阱区重叠的埋入电极，与埋入电极连接并埋设在基板中的多个栅极，使得它们各自与源极区相邻， 栅极互连设置在所述衬底上以在平面图中与所述外围周边阱区域的一部分重叠并连接到所述掩埋电极，以及接地电极，设置在所述衬底上并连接到所述外部周边阱区域的不与所述栅极重叠的部分 在平面图中互连。

公开(公告)号：US20130264637A1

公开(公告)日：2013-10-10

申请号：US13851875

申请日：2013-03-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki KATOU ,  Hiroyoshi KUDOU ,  Taro MORIYA ,  Satoshi UCHIYA

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0865 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/7811 ,  H01L29/7813

Abstract: Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer.

Abstract translation: 沟槽形成在基层中并且彼此平行延伸。 在多个沟槽的每个的内壁上形成栅极绝缘膜。 栅电极GE被埋在每个沟槽中。 源层在基底层中形成到比基底层更深的深度。 源层设置在每个沟槽之间。 在平面图中，在源极层和沟槽之间形成第二导电型高浓度层。 沟槽，源极层和第二导电型高浓度以平面图重复排列。 沟槽的一个侧面面向源极层，沟槽的另一个侧面面向第二导电型高浓度层。