公开(公告)号：US20200044022A1

公开(公告)日：2020-02-06

申请号：US16449350

申请日：2019-06-22

Applicant: Richtek Technology Corporation

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.

公开(公告)号：US20200006490A1

公开(公告)日：2020-01-02

申请号：US16354140

申请日：2019-03-14

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/40 ,  H01L21/74 ,  H01L29/66

Abstract: An N-type high voltage device includes: a semiconductor layer, a well region, a floating region, a bias region, a body region, a body contact, a gate, a source and a drain. The floating region and the bias region both have P-type, and both are formed in a drift region in the well region. The bias region is electrically connected with a predetermined bias voltage, and the floating region is electrically floating, to increase a breakdown voltage of the high voltage device and suppressing turning-ON a parasitic transistor in the high voltage device.

公开(公告)号：US20180342610A1

公开(公告)日：2018-11-29

申请号：US16037981

申请日：2018-07-17

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L21/76205 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

公开(公告)号：US20180315851A1

公开(公告)日：2018-11-01

申请号：US15909277

申请日：2018-03-01

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Ching-Yao Yang

IPC: H01L29/78

Abstract: A high voltage depletion mode MOS device with adjustable threshold voltage includes: a first conductive type well region; a second conductive type channel region, wherein when the channel region is not depleted, the MOS device is conductive, and when the channel region is depleted, the MOS device is non-conductive; a second conductive type connection region which contacts the channel region; a first conductive type gate, for controlling the conductive condition of the MOS device; a second conductive type lightly doped diffusion region formed under a spacer layer of the gate and contacting the channel region; a second type source region; and a second type drain region contacting the connection region but not contacting the gate; wherein the gate has a first conductive type doping or both a first and a second conductive type doping, and wherein a net doping concentration of the gate is determined by a threshold voltage target.

公开(公告)号：US20180190819A1

公开(公告)日：2018-07-05

申请号：US15585949

申请日：2017-05-03

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/7834 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/6659 ,  H01L29/66636

Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.

公开(公告)号：US20160380093A1

公开(公告)日：2016-12-29

申请号：US15260599

申请日：2016-09-09

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chien-Wei Chiu

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/10 ,  H01L23/535 ,  H01L29/08 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L23/481 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0843 ,  H01L29/1004 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/66212 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/66333 ,  H01L29/66462 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

Abstract translation: 本发明公开了一种立式半导体器件及其制造方法。 所述垂直半导体器件包括：具有第一表面和第二表面的衬底，所述衬底包括由穿过所述衬底的多个导电插塞形成的导电阵列; 形成在所述第一表面上的半导体层，所述半导体层具有第三表面和第四表面，其中所述第四表面面向所述第一表面; 形成在第三表面上的第一电极; 以及形成在所述第二表面上用于电连接到所述导电阵列的第二电极。

公开(公告)号：US09093463B1

公开(公告)日：2015-07-28

申请号：US14537424

申请日：2014-11-10

Applicant: Richtek Technology Corporation

Inventor： Chung-Yu Hung ,  Jian-Hsing Lee ,  Tzu-Cheng Kao ,  Tsung-Yi Huang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/66393 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/737 ,  H01L29/87

Abstract: A silicon controlled rectifier includes: a substrate; a N well and a P well positioned on a side of the substrate and contact with each other; a first N region and a first P region positioned on an upper surface of the N well and contact with each other; a second N region and a second P region positioned on an upper surface of the P well and contact with each other; a first oxide isolation region isolating the first P region and the second N region; a second oxide isolation region isolating the second N region and the second P region; an anode terminal coupled with the first N region and the first P region; and a cathode terminal coupled with the second N region and the second P region. The first P region has a doping concentration less than 80% of that of the second P region.

Abstract translation: 可控硅整流器包括：基板; N阱和P阱定位在基板的一侧并彼此接触; 第一N区和第一P区，位于N阱的上表面并彼此接触; 第二N区和第二P区，位于P阱的上表面并彼此接触; 隔离所述第一P区和所述第二N区的第一氧化物隔离区; 隔离所述第二N区域和所述第二P区域的第二氧化物隔离区域; 与所述第一N区和所述第一P区耦合的阳极端; 以及与第二N区域和第二P区域耦合的阴极端子。 第一P区的掺杂浓度小于第二P区的掺杂浓度的80％。

公开(公告)号：US11171232B2

公开(公告)日：2021-11-09

申请号：US16711383

申请日：2019-12-11

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: A high voltage device for use as a lower switch in a power stage of a switching regulator includes at least one lateral diffused metal oxide semiconductor (LDMOS) device and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well, a body region, a gate, a source, and a drain. The SBD includes a Schottky metal layer and a Schottky semiconductor layer. The Schottky metal layer is electrically connected to the source, and the Schottky semiconductor layer is in contact with the well.

公开(公告)号：US10998404B2

公开(公告)日：2021-05-04

申请号：US16503509

申请日：2019-07-04

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/74 ,  H01L29/78

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.

公开(公告)号：US20200052072A1

公开(公告)日：2020-02-13

申请号：US16503509

申请日：2019-07-04

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/74 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.