公开(公告)号：US08373209B2

公开(公告)日：2013-02-12

申请号：US12974516

申请日：2010-12-21

Applicant: Rajesh Kumar Malhan ,  Naohiro Sugiyama

Inventor： Rajesh Kumar Malhan ,  Naohiro Sugiyama

IPC: H01L29/12

CPC classification number: H01L29/808 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068

Abstract: A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.

Abstract translation: 半导体器件包括：衬底; 以及耗尽和增强型JFET。 耗尽型JFET包括：衬底上的凹面; 凹陷中的沟道层; 沟道层上的第一栅极区; 在沟道层中的第一栅极区域的相应侧上的第一源极和漏极区域; 第一栅极，源极和漏极。 增强模式JFET包括：在衬底上的凸起; 沟道层上凸; 沟道层上的第二栅极区; 在沟道层中的第二栅极区的相应侧上的第二源极和漏极区; 第二栅极，源极和漏极。 凹槽中的沟道层的厚度大于沟槽层的厚度。

公开(公告)号：US20110156053A1

公开(公告)日：2011-06-30

申请号：US12974516

申请日：2010-12-21

Applicant: Rajesh Kumar Malhan ,  Naohiro Sugiyama

Inventor： Rajesh Kumar Malhan ,  Naohiro Sugiyama

IPC: H01L29/12 ,  H01L29/808 ,  H01L21/337

CPC classification number: H01L29/808 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068

Abstract: A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.

Abstract translation: 半导体器件包括：衬底; 以及耗尽和增强型JFET。 耗尽型JFET包括：衬底上的凹面; 凹陷中的沟道层; 沟道层上的第一栅极区; 在沟道层中的第一栅极区域的相应侧上的第一源极和漏极区域; 第一栅极，源极和漏极。 增强模式JFET包括：在衬底上的凸起; 沟道层上凸; 沟道层上的第二栅极区; 在沟道层中的第二栅极区的相应侧上的第二源极和漏极区; 第二栅极，源极和漏极。 凹槽中的沟道层的厚度大于沟槽层的厚度。

公开(公告)号：US07557434B2

公开(公告)日：2009-07-07

申请号：US11511517

申请日：2006-08-29

Applicant: Rajesh Kumar Malhan ,  C. Mark Johnson ,  Jeremy Rashid

Inventor： Rajesh Kumar Malhan ,  C. Mark Johnson ,  Jeremy Rashid

IPC: H01L23/02

CPC classification number: H01L24/72 ,  H01L24/01 ,  H01L24/33 ,  H01L25/072 ,  H01L25/18 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions. The mechanical separation provides a net axially-directed compressive force in the electronic components.

Abstract translation: 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及安装在每个基板上的多个电子部件。 基板在多个接合区域彼此耦合，使得基板之间的机械分离由接合区域的数量，接合区域的布置，每个接合区域的形状和接合区域的材料 。 机械分离在电子部件中提供净轴向定向的压缩力。

公开(公告)号：US08748948B2

公开(公告)日：2014-06-10

申请号：US13012123

申请日：2011-01-24

Applicant: Rajesh Kumar Malhan

Inventor： Rajesh Kumar Malhan

IPC: H01L29/80 ,  H01L31/0312

CPC classification number: H01L29/808 ,  H01L21/7602 ,  H01L21/8213 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/66068

Abstract: A SiC semiconductor device includes: a SiC substrate made of intrinsic SiC having semi-insulating property; first and second conductive type SiC layers disposed in the substrate; an insulation separation layer made of intrinsic SiC for isolating the first conductive type SiC layer from the second conductive type SiC layer; first and second conductive type channel JFETs disposed in the first and second conductive type SiC layers, respectively. The first and second conductive type channel JFETs provide a complementary junction field effect transistor. Since an electric element is formed on a flat surface, a manufacturing method is simplified. Further, noise propagation at high frequency and current leakage at high temperature are restricted.

Abstract translation: SiC半导体器件包括：由具有半绝缘性的本征SiC制成的SiC衬底; 设置在基板中的第一和第二导电型SiC层; 由本征SiC制成的绝缘分离层，用于将第一导电型SiC层与第二导电型SiC层隔离; 分别设置在第一和第二导电型SiC层中的第一和第二导电型沟道JFET。 第一和第二导电型沟道JFET提供互补结型场效应晶体管。 由于电气元件形成在平坦表面上，所以制造方法简单。 此外，高频下的噪声传播和高温下的电流泄漏受到限制。

公开(公告)号：US08519452B2

公开(公告)日：2013-08-27

申请号：US13248173

申请日：2011-09-29

Applicant: Rajesh Kumar Malhan

Inventor： Rajesh Kumar Malhan

IPC: H01L29/812 ,  H01L21/337 ,  H01L29/768

CPC classification number: H01L29/8083 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/872

Abstract: A semiconductor device with a JFET is disclosed. The semiconductor device includes a trench and a contact embedded layer formed in the trench. A gate wire is connected to the contact embedded layer, so that the gate wire is connected to an embedded gate layer via the contact embedded layer. In this configuration, it is possible to downsize a contact structure between the embedded gate layer and the gate wire.

Abstract translation: 公开了一种具有JFET的半导体器件。 半导体器件包括形成在沟槽中的沟槽和接触嵌入层。 栅极线连接到触点嵌入层，使得栅极线经由接触嵌入层连接到嵌入式栅极层。 在这种结构中，可以减小嵌入式栅极层与栅极线之间的接触结构。

公开(公告)号：US08274086B2

公开(公告)日：2012-09-25

申请号：US12458968

申请日：2009-07-28

Applicant: Rajesh Kumar Malhan ,  Yuuichi Takeuchi ,  Jeremy Rashid

Inventor： Rajesh Kumar Malhan ,  Yuuichi Takeuchi ,  Jeremy Rashid

IPC: H01L29/15 ,  H01L31/0256

CPC classification number: H01L29/8083 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/6609 ,  H01L29/66325 ,  H01L29/8611 ,  H01L29/872

Abstract: A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.

Abstract translation: 宽带隙半导体器件具有晶体管单元区域，二极管形成区域，位于晶体管单元区域和二极管形成区域之间的电场弛豫区域以及围绕晶体管单元区域和二极管形成区域的外围区域。 在晶体管单元区域中，设置结型场效应晶体管。 在二极管形成区域中，设置二极管。 在电场弛豫区域中，设置隔离部。 隔离部分包括分隔晶体管单元区域和二极管形成区域的沟槽，设置在沟槽的内壁上的第一导电类型层和设置在第一导电类型层的表面上的第二导电类型层 以填补沟槽。 第一导电型层和第二导电型层提供PN结。

公开(公告)号：US08194392B2

公开(公告)日：2012-06-05

申请号：US12830517

申请日：2010-07-06

Applicant: Rajesh Kumar Malhan ,  Naohiro Sugiyama ,  Yuji Noguchi ,  Masaru Miyayama

Inventor： Rajesh Kumar Malhan ,  Naohiro Sugiyama ,  Yuji Noguchi ,  Masaru Miyayama

IPC: H01G4/06

CPC classification number: H01G4/1227 ,  C04B35/4682 ,  C04B35/49 ,  C04B35/495 ,  C04B2235/3206 ,  C04B2235/3215 ,  C04B2235/3236 ,  C04B2235/3255 ,  C04B2235/3279 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/656 ,  C04B2235/6567 ,  C04B2235/662 ,  C04B2235/77 ,  C04B2235/81 ,  H01G4/0085 ,  H01G4/30

Abstract: A ceramic material has a perovskite structure and is represented by formula of (1−x)ABO3-xYZO3. In the formula, “x” is a real number that is greater than 0 and is less than 1 each of “A,” “B,” “Y,” and “Z” is one or more kinds selected from a plurality of metal ions M other than a Pb ion and alkali metal ions, “A” is bivalent, “B” is tetravalent, “Y” is trivalent or combination of trivalent metal ions, and “Z” is bivalent and/or trivalent metal ions, or a bivalent and/or pentavalent metal ions.

Abstract translation: 陶瓷材料具有钙钛矿结构并由（1-x）ABO 3-x YZO 3的式表示。 在该公式中，“x”是大于0并且小于“A”，“B”，“Y”“的1的实数，”Z“是从多个金属中选择的一种或多种 离子M除了Pb离子和碱金属离子之外，“A”为二价，“B”为四价，“Y”为三价金属离子或三价金属离子的组合，“Z”为二价和/或三价金属离子，或 二价和/或五价金属离子。

公开(公告)号：US07999369B2

公开(公告)日：2011-08-16

申请号：US11511516

申请日：2006-08-29

Applicant: Rajesh Kumar Malhan ,  C. Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

Inventor： Rajesh Kumar Malhan ,  C. Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

IPC: H01L23/48

CPC classification number: H01L23/49844 ,  H01L23/5385 ,  H01L24/31 ,  H01L24/83 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/33 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

Abstract translation: 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。

公开(公告)号：US20110156054A1

公开(公告)日：2011-06-30

申请号：US12976116

申请日：2010-12-22

Applicant: Yuuichi TAKEUCHI ,  Rajesh Kumar Malhan ,  Naohiro Sugiyama

Inventor： Yuuichi TAKEUCHI ,  Rajesh Kumar Malhan ,  Naohiro Sugiyama

IPC: H01L29/24 ,  H01L21/337 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828

Abstract: A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.

Abstract translation: 具有JFET或MOSFET的碳化硅半导体器件包括半导体衬底和沟槽。 半导体衬底具有碳化硅衬底，碳化硅衬底上的漂移层，漂移层上的第一栅极区域和第一栅极区域上的源极区域。 沟槽具有纵向方向的带状，并通过穿透源极区域和第一栅极区域而到达漂移层。 在沟道层上填充沟道层和第二栅极区域。 源极区域不位于沟槽的纵向方向的端部。

公开(公告)号：US20110156052A1

公开(公告)日：2011-06-30

申请号：US12926894

申请日：2010-12-16

Applicant: Rajesh Kumar Malhan ,  Yuuichi Takeuchi ,  Naohiro Sugiyama

Inventor： Rajesh Kumar Malhan ,  Yuuichi Takeuchi ,  Naohiro Sugiyama

IPC: H01L29/24 ,  H01L29/80 ,  H01L21/337

CPC classification number: H01L29/808 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068

Abstract: A semiconductor device having a JFET includes: a substrate made of semi-insulating semiconductor material; a gate region in a surface portion of the substrate; a channel region disposed on and contacting the gate region; a source region and a drain region disposed on both sides of the gate region so as to sandwich the channel region, respectively; a source electrode electrically coupled with the source region; a drain electrode electrically coupled with the drain region; and a gate electrode electrically coupled with the gate region. An impurity concentration of each of the source region and the drain region is higher than an impurity concentration of the channel region.

Abstract translation: 具有JFET的半导体器件包括：由半绝缘半导体材料制成的衬底; 在所述基板的表面部分中的栅极区域; 设置在栅区上并与其接触的沟道区; 源极区域和漏极区域，分别设置在栅极区域的两侧，以夹持沟道区域; 源极，与源极电耦合; 漏极，与漏极区电耦合; 以及与栅极区域电耦合的栅电极。 源极区域和漏极区域中的每一个的杂质浓度高于沟道区域的杂质浓度。