公开(公告)号：US07307313B2

公开(公告)日：2007-12-11

申请号：US11206212

申请日：2005-08-18

Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Kumar Malhan

Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Kumar Malhan

IPC: H01L29/76

CPC classification number: H01L29/1066 ,  H01L29/7722 ,  H01L29/8083

Abstract: A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.

Abstract translation: 半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽， 沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极 控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管， 在第二沟槽之间的第二表面上形成的结。

公开(公告)号：US07241694B2

公开(公告)日：2007-07-10

申请号：US11105587

申请日：2005-04-14

Applicant: Yuuichi Takeuchi ,  Rajesh Kumar Malhan ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

Inventor： Yuuichi Takeuchi ,  Rajesh Kumar Malhan ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC: H01L21/18 ,  H01L21/302 ,  H01L21/308

CPC classification number: H01L29/045 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/8083

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.

Abstract translation: 一种制造碳化硅半导体器件的方法包括以下步骤：在半导体衬底的上表面上形成沟槽掩模; 形成沟槽，使得形成具有等于或大于2并且具有等于或大于80度的沟槽倾斜角的纵横比的沟槽; 并且以这样的方式去除损伤部分，即在形成沟槽的步骤中形成在半导体衬底的沟槽的内表面上的损伤部分在氢气气氛中在等于或等于更高的温度的减压下被蚀刻和去除 比1600℃

公开(公告)号：US07141498B2

公开(公告)日：2006-11-28

申请号：US11159264

申请日：2005-06-23

Applicant: Rajesh Kumar Malhan ,  Yuichi Takeuchi ,  Irina Nikitina ,  Konstantin Vassilevski ,  Nicholas Wright ,  Alton Horsfall

Inventor： Rajesh Kumar Malhan ,  Yuichi Takeuchi ,  Irina Nikitina ,  Konstantin Vassilevski ,  Nicholas Wright ,  Alton Horsfall

IPC: H01L21/44

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395

Abstract: A method of forming an ohmic contact on a substrate composed of a wide-band gap semiconductor material includes: depositing a transition metal group metal on the substrate; annealing the substrate at a high temperature to cause a solid state chemical reaction between the substrate and the deposited metal that forms a modified layer in the substrate having modified properties different than the substrate, and by-products composed of a silicide and a nanocrystalline graphite layer; selectively etching the substrate to remove one or more of the by-products of the solid state chemical reaction from a surface of the substrate; and depositing a metal film composed of a transition group metal over the modified layer on the substrate to form the ohmic contact. The modified layer permits formation of the ohmic contact without high temperature annealing after depositing the metal film.

公开(公告)号：US08575648B2

公开(公告)日：2013-11-05

申请号：US12976116

申请日：2010-12-22

Applicant: Yuuichi Takeuchi ,  Rajesh Kumar Malhan ,  Naohiro Sugiyama

Inventor： Yuuichi Takeuchi ,  Rajesh Kumar Malhan ,  Naohiro Sugiyama

IPC: H01L29/423 ,  H01L21/337

CPC classification number: H01L29/0847 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828

Abstract: A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.

Abstract translation: 具有JFET或MOSFET的碳化硅半导体器件包括半导体衬底和沟槽。 半导体衬底具有碳化硅衬底，碳化硅衬底上的漂移层，漂移层上的第一栅极区域和第一栅极区域上的源极区域。 沟槽具有纵向方向的带状，并通过穿透源极区域和第一栅极区域而到达漂移层。 在沟道层上填充沟道层和第二栅极区域。 源极区域不位于沟槽的纵向方向的端部。

公开(公告)号：US20080054439A1

公开(公告)日：2008-03-06

申请号：US11511516

申请日：2006-08-29

Applicant: Rajesh Kumar Malhan ,  C. Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

Inventor： Rajesh Kumar Malhan ,  C. Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

IPC: H01L23/48

CPC classification number: H01L23/49844 ,  H01L23/5385 ,  H01L24/31 ,  H01L24/83 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/33 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

Abstract translation: 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。

公开(公告)号：US20080054425A1

公开(公告)日：2008-03-06

申请号：US11511517

申请日：2006-08-29

Applicant: Rajesh Kumar Malhan ,  C. Mark Johnson ,  Jeremy Rashid

Inventor： Rajesh Kumar Malhan ,  C. Mark Johnson ,  Jeremy Rashid

IPC: H01L23/02

CPC classification number: H01L24/72 ,  H01L24/01 ,  H01L24/33 ,  H01L25/072 ,  H01L25/18 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions. The mechanical separation provides a net axially-directed compressive force in the electronic components.

Abstract translation: 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及安装在每个基板上的多个电子部件。 基板在多个接合区域彼此耦合，使得基板之间的机械分离由接合区域的数量，接合区域的布置，每个接合区域的形状以及接合区域的材料 。 机械分离在电子部件中提供净轴向定向的压缩力。

公开(公告)号：US07335928B2

公开(公告)日：2008-02-26

申请号：US11802810

申请日：2007-05-25

Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Kumar Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Kumar Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

IPC: H01L29/74 ,  H01L31/111

CPC classification number: H01L29/66416 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/8083

Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

Abstract translation: 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。

公开(公告)号：US07230283B2

公开(公告)日：2007-06-12

申请号：US11138298

申请日：2005-05-27

Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Kumar Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Kumar Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

IPC: H01L29/74 ,  H01L31/111

CPC classification number: H01L29/66416 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/8083

Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

Abstract translation: 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。

公开(公告)号：US08604540B2

公开(公告)日：2013-12-10

申请号：US12956152

申请日：2010-11-30

Applicant: Rajesh Kumar Malhan ,  Naohiro Sugiyama ,  Yuuichi Takeuchi

Inventor： Rajesh Kumar Malhan ,  Naohiro Sugiyama ,  Yuuichi Takeuchi

IPC: H01L29/66 ,  H01L21/337

CPC classification number: H01L29/808 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/8128

Abstract: A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.

Abstract translation: 具有JFET，MESFET或MOSFET的宽带隙半导体器件主要包括半导体衬底，第一导电类型半导体层和第一导电型沟道层。 半导体层形成在基板的主表面上。 在半导体层中以半导体层被分成源极区和漏极区的方式形成凹部。 凹部具有由基板的主表面和由半导体层限定的侧壁限定的底部。 沟道层的杂质浓度低于半导体层的杂质浓度。 沟槽层通过外延生长形成在凹部的底部和侧壁上。

公开(公告)号：US08432030B2

公开(公告)日：2013-04-30

申请号：US13171788

申请日：2011-06-29

Applicant: Rajesh Kumar Malhan ,  C Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

Inventor： Rajesh Kumar Malhan ,  C Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

IPC: H01L23/48

CPC classification number: H01L23/49844 ,  H01L23/5385 ,  H01L24/31 ,  H01L24/83 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/33 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

Abstract translation: 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。