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公开(公告)号：US06440793B1
公开(公告)日：2002-08-27
申请号：US09757514
申请日：2001-01-10
IPC分类号： H01L218242
CPC分类号： H01L27/10841 , H01L21/2255 , H01L21/26586 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
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12.发明授权Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效在单元中并联连接沟槽电容器的多端口存储器制造方法公开(公告)号：US07785959B2
公开(公告)日：2010-08-31
申请号：US12316748
申请日：2008-12-16
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译： 提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。 形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。 第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。 以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。
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13.发明授权Memory cell with vertical transistor and trench capacitor with reduced burried strap 有权具有垂直晶体管和沟槽电容器的存储单元，具有减少的挂带公开(公告)号：US06759702B2
公开(公告)日：2004-07-06
申请号：US10261559
申请日：2002-09-30
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/66181 , H01L29/945
摘要： A memory cell structure including a semiconductor substrate, a deep (e.g., longitudinal) trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a buried strap along a sidewall of the deep trench, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down the sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down another sidewall of the deep trench opposite the capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, and a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions. The deep trench has a perimeter in a direction normal to its depth, and the buried strap extends a distance along the perimeter, the distance being only within a range of 5% to 20% of the entire linear distance along the perimeter, and being less than one lithographic feature size. Preferably, the strap in a direction along the perimeter is curved and is disposed along only one corner of the perimeter. The structure is particularly useful for a sub-8F2 cell.
摘要翻译： 一种存储单元结构，包括半导体衬底，半导体衬底中的深（例如，纵向）沟槽，深沟槽具有多个侧壁和底部，沿着深沟槽的侧壁的掩埋带，存储电容器 深沟槽的底部，垂直晶体管，沿着存储电容器上方的深沟槽的侧壁向下延伸，晶体管具有在衬底的与深沟槽相邻的平面中延伸的扩散，从深沟槽的另一个侧壁延伸的环状氧化物 与电容器相对的浅沟槽隔离区域沿垂直于垂直晶体管延伸的侧壁横向的衬底表面延伸，在深沟槽内延伸的栅极导体，延伸在深沟槽上并与栅极导体连接的字线 以及在衬底的表面平面上方延伸的位线，该位线与浅沟槽iso之间的扩散接触 国际地区。 深沟槽在垂直于其深度的方向上具有周长，并且掩埋带沿着周边延伸一段距离，该距离仅在沿着周边的整个线性距离的5％至20％的范围内，并且更小 比一个光刻特征尺寸。 优选地，沿着周边的方向上的带子是弯曲的并且沿着周边的一个角部设置。 该结构对于亚8F 2细胞特别有用。
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14.发明授权公开(公告)号：US06339241B1
公开(公告)日：2002-01-15
申请号：US09602426
申请日：2000-06-23
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.
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15.发明授权Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell 失效制造在单元中具有多个并联连接的沟槽电容器的多端口存储器的方法公开(公告)号：US07485525B2
公开(公告)日：2009-02-03
申请号：US11306749
申请日：2006-01-10
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.
摘要翻译： 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。 这种存储器包括存储单元的阵列，其中每个存储单元包括连接在一起作为整体电容源的多个电容器。 第一存取晶体管耦合在多个电容器中的第一电容器和第一位线之间，第二存取晶体管耦合在多个电容器中的第二电容器和第二位线之间。 在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。
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16.发明授权Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI 失效用于制造具有双门控垂直MOSFET和自对准STI的6F2沟槽DRAM单元的方法公开(公告)号：US06808981B2
公开(公告)日：2004-10-26
申请号：US10375654
申请日：2003-02-27
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/823481 , H01L21/823487
摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.
摘要翻译： 提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与单元的字线和位线自对准的区域）的存储单元。 本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。 还提供了制造本发明的存储单元的方法。
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17.发明授权6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI 失效6F2沟槽EDRAM单元，具有双门控垂直MOSFET和自对准STI公开(公告)号：US06570208B2
公开(公告)日：2003-05-27
申请号：US09766013
申请日：2001-01-18
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/823481 , H01L21/823487
摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.
摘要翻译： 提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与电池的字线和位线自对准的区域）的存储单元。 本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。 还提供了制造本发明的存储单元的方法。
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公开(公告)号：US06501117B1
公开(公告)日：2002-12-31
申请号：US10007846
申请日：2001-11-05
IPC分类号： H01L27108
CPC分类号： H01L27/11 , G11C11/404 , H01L27/10841 , H01L27/10864 , H01L27/10867 , H01L29/945
摘要： A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT. A peripheral gate oxide layer, which coats sidewalls of the DT above the TTO, defines a space which is filled with the FET gate electrode. An outdiffusion region, doped with the first dopant type, is formed in the well region near the buried-strap. The cell has a first state and an opposite state of operation. A punch-through device, formed in the well between the outdiffusion region and the interface, provides a self-refreshing punchthrough current in the cell between the well and the plate in the first state of cell operation. A reverse bias junction leakage current occurs in the cell between the buried-strap and the P-well to refresh the opposite state of cell operation.
摘要翻译： 在FET晶体管下方的深沟槽（DT）的底部形成DRAM单元存储电容器。 DT具有具有侧壁的上部，中部和下部。 围绕掺杂有第一掺杂剂类型的下部DT部分的电容器平板电极通过界面与围绕掺杂有相反掺杂剂类型的DT的上部和中部的阱区隔开。 形成在电池顶部的源极/漏极区掺杂有第一掺杂剂类型。 覆盖DT的下部和中心部分的侧壁和底部的节点电介质层填充有掺杂有第一掺杂剂类型的电容器的节点电极，填充第一掺杂剂类型的下部的节点电介质层内部的空间 DT。 在凹陷节点电介质层上方，带区域空间填充有埋地导体。 在DT上的节点电极和掩埋带上形成氧化物（TTO）层。 在TTO上方覆盖DT的侧壁的外围栅极氧化物层限定了用FET栅电极填充的空间。 在掩埋带附近的阱区中形成掺杂有第一掺杂剂类型的扩散区。 电池具有第一状态和相反的操作状态。 形成在扩散区域和界面之间的井中的穿通装置在电池操作的第一状态下在孔和板之间的电池单元中提供自刷新穿透电流。 在埋层和P阱之间的电池中产生反向偏置结漏电流，以刷新电池操作的相反状态。
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19.发明授权Method for shallow trench isolated, contacted well, vertical MOSFET DRAM 失效浅沟槽隔离方法，接触良好，垂直MOSFET DRAM公开(公告)号：US06284593B1
公开(公告)日：2001-09-04
申请号：US09705652
申请日：2000-11-03
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.
摘要翻译： 提供了形成混合存储器单元的过程，该混合存储器单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。
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公开(公告)号：US20090047756A1
公开(公告)日：2009-02-19
申请号：US12254960
申请日：2008-10-21
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。
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