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公开(公告)号：US20180330769A1
公开(公告)日：2018-11-15
申请号：US15978344
申请日：2018-05-14
Applicant: Rambus Inc.
Inventor： Christopher HAYWOOD , David WANG
CPC classification number: G11C7/1072 , G06F11/073 , G06F11/0778 , G06F11/0787 , G06F11/1008 , G06F11/1044 , G06F11/1048 , G06F11/1068 , G11C5/04 , G11C7/1006 , G11C29/52 , G11C2029/0411
Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.
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Patent Agency Ranking
公开(公告)号：US20170185489A1
公开(公告)日：2017-06-29
申请号：US15401985
申请日：2017-01-09
Applicant: Rambus Inc.
Inventor： Shih-ho WU , Christopher HAYWOOD
CPC classification number: G06F3/0647 , G06F3/0619 , G06F3/0683 , G06F3/0688 , G06F11/1441 , G06F11/1458 , G06F11/1469 , G06F11/1662 , G06F11/1666 , G06F11/2015 , G06F12/0246 , G06F12/0868 , G06F2201/83 , G06F2212/1016 , G06F2212/1032 , G06F2212/7203 , G06F2212/7207 , G06F2212/7209 , G11C14/0009 , Y02D10/13
Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.
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公开(公告)号：US20240096434A1
公开(公告)日：2024-03-21
申请号：US18373799
申请日：2023-09-27
Applicant: Rambus Inc.
Inventor： Christopher HAYWOOD
CPC classification number: G11C29/44 , G11C7/22 , G11C29/12015 , G11C29/18 , G11C29/702 , G11C2029/1806
Abstract: Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.
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公开(公告)号：US20210390066A1
公开(公告)日：2021-12-16
申请号：US17333420
申请日：2021-05-28
Applicant: Rambus Inc.
Inventor： Christopher HAYWOOD , Evan Lawrence ERICKSON
Abstract: A multi-path fabric interconnected system with many nodes and many communication paths from a given source node to a given destination node. A memory allocation device on an originating node (local node) requests an allocation of memory from a remote node (i.e., requests a remote allocation). The memory allocation device on the local node selects the remote node based on one or more performance indicators. The local memory allocation device may select the remote node to provide a remote allocation of memory based on one or more of: latency, availability, multi-path bandwidth, data access patterns (both local and remote), fabric congestion, allowed bandwidth limits, maximum latency limits, and, available memory on remote node.
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公开(公告)号：US20210389887A1
公开(公告)日：2021-12-16
申请号：US17333409
申请日：2021-05-28
Applicant: Rambus Inc.
Inventor： Evan Lawrence ERICKSON , Christopher HAYWOOD
IPC: G06F3/06
Abstract: A memory allocation device on an originating node requests an allocation of memory from a remote node. In response, the memory allocation device on the remote node returns a global system address that can be used to access the remote allocation from the originating node. Concurrent with the memory allocation device assigning (associating) a local (to its node) physical address to be used to access the remote allocation, the remote node allocates local physical memory to fulfill the remote allocation request. In this manner, the remote node has already completed the overhead operations associated with the remote allocation requested by the time the remote allocation is accessed by the originating node.
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公开(公告)号：US20200312420A1
公开(公告)日：2020-10-01
申请号：US16823908
申请日：2020-03-19
Applicant: Rambus Inc.
Inventor： Christopher HAYWOOD
Abstract: Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.
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