公开(公告)号：US09563228B2

公开(公告)日：2017-02-07

申请号：US14954940

申请日：2015-11-30

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F1/04 ,  G06F1/10 ,  G06F13/16 ,  G11C7/22 ,  G06F1/06 ,  G06F1/08 ,  H04L7/033 ,  G11C7/04

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract translation: 存储器控制器包括时钟发生器，用于产生第一时钟信号和定时电路，以从第一时钟信号产生第二时钟信号。 第二时钟信号与相应等级中的多个存储器件中的任何一个存储器件进行通信，包括第一等级中的第一存储器件和第二等级的第二存储器件。 定时电路被配置为基于与第二存储器设备相关联的校准数据和与来自至少第一存储器的反馈相关联的定时调整数据来调整存储器控制器与第二存储器件通信时的第一时钟信号的相位 设备。

公开(公告)号：US20160116938A1

公开(公告)日：2016-04-28

申请号：US14954940

申请日：2015-11-30

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F1/10 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract translation: 存储器控制器包括时钟发生器，用于产生第一时钟信号和定时电路，以从第一时钟信号产生第二时钟信号。 第二时钟信号与相应等级中的多个存储器件中的任何一个存储器件进行通信，包括第一等级中的第一存储器件和第二等级的第二存储器件。 定时电路被配置为基于与第二存储器设备相关联的校准数据和与来自至少第一存储器的反馈相关联的定时调整数据来调整存储器控制器与第二存储器件通信时的第一时钟信号的相位 设备。