公开(公告)号：US20230359572A1

公开(公告)日：2023-11-09

申请号：US18135095

申请日：2023-04-14

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G11C7/22 ,  G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  G06F1/08 ,  G06F13/16

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/222 ,  G11C7/04

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US11630788B2

公开(公告)日：2023-04-18

申请号：US16921061

申请日：2020-07-06

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G11C7/22 ,  G06F1/10 ,  G06F1/06 ,  G06F1/08 ,  G06F1/04 ,  G11C7/04 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US20190196992A1

公开(公告)日：2019-06-27

申请号：US16228695

申请日：2018-12-20

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US20250053524A1

公开(公告)日：2025-02-13

申请号：US18807548

申请日：2024-08-16

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G11C7/04 ,  G11C7/22 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US20230112159A1

公开(公告)日：2023-04-13

申请号：US17962362

申请日：2022-10-07

Applicant: Rambus Inc.

Inventor： Lei Luo ,  John Eble

IPC: G06F3/06

Abstract: Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes conversion circuitry to down-convert the first data at the quad data rate to the second data at the first specified data rate and up-convert the second data at the first specified data rate to the first data at the quad data rate.

公开(公告)号：US10162772B2

公开(公告)日：2018-12-25

申请号：US15424714

申请日：2017-02-03

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F1/04 ,  G06F1/10 ,  G06F13/16 ,  G11C7/22 ,  G06F1/06 ,  G06F1/08 ,  H04L7/033 ,  G11C7/04

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US20170192912A1

公开(公告)日：2017-07-06

申请号：US15424714

申请日：2017-02-03

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/06 ,  G06F1/10 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US12066958B2

公开(公告)日：2024-08-20

申请号：US18135095

申请日：2023-04-14

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G11C7/22 ,  G11C7/04 ,  H04L7/033

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/222 ,  G11C7/04 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US20210049118A1

公开(公告)日：2021-02-18

申请号：US16921061

申请日：2020-07-06

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/10 ,  G11C7/22 ,  G06F1/06 ,  G06F1/08 ,  G06F1/04

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US10705990B2

公开(公告)日：2020-07-07

申请号：US16228695

申请日：2018-12-20

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/16 ,  G11C7/22 ,  G11C7/04 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.