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公开(公告)号：US20240212739A1
公开(公告)日：2024-06-27
申请号：US18403569
申请日：2024-01-03
Applicant: Rambus Inc.
Inventor： Torsten PARTSCH , John Eric LINSTADT , Helena HANDSCHUH
IPC: G11C11/406 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C11/4094
CPC classification number: G11C11/40626 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094
Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.
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公开(公告)号：US20210303383A1
公开(公告)日：2021-09-30
申请号：US17236445
申请日：2021-04-21
Applicant: Rambus Inc.
Inventor： Thomas J. GIOVANNINI , Catherine CHEN , Scott C. BEST , John Eric LINSTADT , Frederick A. WARE
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号：US20190179690A1
公开(公告)日：2019-06-13
申请号：US16183470
申请日：2018-11-07
Applicant: Rambus Inc.
Inventor： Thomas J. GIOVANNINI , Catherine CHEN , Scott C. BEST , John Eric LINSTADT , Frederick A. WARE
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号：US20180357125A1
公开(公告)日：2018-12-13
申请号：US15990078
申请日：2018-05-25
Applicant: Rambus Inc.
Inventor： Michael MILLER , Stephen MAGEE , John Eric LINSTADT
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0625 , G06F3/0644 , G06F3/0673 , G06F11/1048
Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.
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公开(公告)号：US20250045197A1
公开(公告)日：2025-02-06
申请号：US18775487
申请日：2024-07-17
Applicant: Rambus Inc.
Inventor： John Eric LINSTADT , Thomas VOGELSANG
IPC: G06F12/02
Abstract: A memory device includes functionality (e.g., mode, command, etc.) to concurrently activate/access a plurality of rows across a corresponding plurality of memory banks. When concurrently accessing the memory banks, the row address and column address are provided to all of the memory banks being accessed. Multiplexer/demultiplexer (e.g., steering logic) may be used to route non-payload (e.g., metadata) from the concurrently activated memory banks to/from the data interface of the memory device. The steering logic may route and/or serialize the metadata from the concurrently activated memory banks of the bank group such that the non-payload data from a respective memory bank is communicated via the same data signal(s) (e.g., DQ[0], DQ[1], etc.) of the data interface.
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Patent Agency Ranking
公开(公告)号：US20240281154A1
公开(公告)日：2024-08-22
申请号：US18569518
申请日：2022-06-21
Applicant: Rambus Inc.
Inventor： Thomas VOGELSANG , Torsten PARTSCH , Brent Steven HAUKNESS , John Eric LINSTADT
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/0659 , G06F3/0673
Abstract: DRAM cells need to be periodically refreshed to preserve the charge stored in them. The retention time is typically not the same for all DRAM cells but follows a distribution with multiple orders of magnitude difference between the retention time of cells with the highest charge loss and the cells with the lowest charge loss. Different refresh intervals are used for certain wordlines based on the required minimum retention time of the cells on those wordlines. The memory controller does not keep track of refresh addresses. After initialization of the DRAM devices, the memory controller issues a smaller number of refresh commands when compared to refreshing all wordlines at the same refresh interval.
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公开(公告)号：US20230317196A1
公开(公告)日：2023-10-05
申请号：US18121220
申请日：2023-03-14
Applicant: Rambus Inc.
Inventor： John Eric LINSTADT , Frederick A. WARE
Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.
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公开(公告)号：US20230260564A1
公开(公告)日：2023-08-17
申请号：US18104069
申请日：2023-01-31
Applicant: Rambus Inc.
Inventor： Torsten PARTSCH , John Eric LINSTADT , Helena HANDSCHUH
IPC: G11C11/406 , G11C11/4091 , G11C11/4076 , G11C11/4094 , G11C11/408
CPC classification number: G11C11/40626 , G11C11/4091 , G11C11/4076 , G11C11/4094 , G11C11/4085
Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.
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公开(公告)号：US20230026876A1
公开(公告)日：2023-01-26
申请号：US17785269
申请日：2020-12-03
Applicant: Rambus Inc.
Inventor： Liji GOPALAKRISHNAN , Thomas VOGELSANG , John Eric LINSTADT
IPC: G06F3/06 , G11C11/406
Abstract: A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.
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公开(公告)号：US20220343992A1
公开(公告)日：2022-10-27
申请号：US17746674
申请日：2022-05-17
Applicant: Rambus Inc.
Inventor： John Eric LINSTADT , Frederick A. WARE
Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.
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