公开(公告)号：US20150234707A1

公开(公告)日：2015-08-20

申请号：US14692092

申请日：2015-04-21

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

IPC: G06F11/10 ,  G11C29/44

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

公开(公告)号：US09037949B1

公开(公告)日：2015-05-19

申请号：US13846200

申请日：2013-03-18

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

公开(公告)号：US20250054561A1

公开(公告)日：2025-02-13

申请号：US18809250

申请日：2024-08-19

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: G11C29/50 ,  G01R23/02 ,  G01R23/15 ,  G01R35/00 ,  G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  G06F13/16 ,  G11C7/04 ,  G11C7/22 ,  G11C8/18 ,  G11C29/02 ,  H03L1/02

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

公开(公告)号：US20240282354A1

公开(公告)日：2024-08-22

申请号：US18590221

申请日：2024-02-28

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/02

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US11948619B2

公开(公告)日：2024-04-02

申请号：US18181185

申请日：2023-03-09

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C7/00 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/02

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20220254407A1

公开(公告)日：2022-08-11

申请号：US17568656

申请日：2022-01-04

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20210174865A1

公开(公告)日：2021-06-10

申请号：US17103374

申请日：2020-11-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C11/4074 ,  G11C7/20 ,  G11C7/02 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US10672450B2

公开(公告)日：2020-06-02

申请号：US16139636

申请日：2018-09-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C8/00 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US10198314B2

公开(公告)日：2019-02-05

申请号：US14285467

申请日：2014-05-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Brent Haukness ,  Scott C. Best ,  Wayne F. Ellis

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C11/40 ,  G11C29/04

Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.

公开(公告)号：US09575835B2

公开(公告)日：2017-02-21

申请号：US14692092

申请日：2015-04-21

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

IPC: G06F11/10 ,  G11C29/44

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。