公开(公告)号：US20050189593A1

公开(公告)日：2005-09-01

申请号：US10787387

申请日：2004-02-26

Applicant: Randy Yach

Inventor： Randy Yach

IPC: H01L27/02 ,  H01L29/87 ,  H01L23/62

CPC classification number: H01L27/0259 ,  Y10S257/917

Abstract: An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure comprises adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer located between the bond pad and the P+ and N+ diffusions. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N− well is located substantially under the N+ and P+ diffusions. The surrounding N+ diffusion partially overlaps the edge of the N− well below it. An outer portion of the N+ diffusion, the portion overlapping the N− well, is within a P− well. The P− well may be the substrate of the integrated circuit. Another N+ diffusion encircles the N+ diffusion surrounding the P+ diffusions. The another N+ diffusion is in the P− well and a field oxide may be located between the N+ diffusion and the another N+ diffusion. An NPN field transistor is formed with the N+ diffusion being the transistor collector, the P− well being the transistor base and the another N+ diffusion being the emitter. The another N+ diffusion (emitter) may be connected to ground by a conductive connection, e.g., metal or low resistance semiconductor material.

Abstract translation: ESD保护结构基本上位于集成电路接合焊盘下方。 该ESD保护结构通过在接合焊盘和ESD钳位电路之间插入正向二极管而形成为低电容结构。 将ESD保护结构放在接合焊盘下方可消除寄生衬底电容，并利用由插入的正向偏置二极管形成的寄生PNP晶体管。 ESD保护结构包括相邻的交替的P +和N +扩散，其基本上位于接合焊盘下面以被ESD保护。 P +扩散通过位于接合焊盘和P +和N +扩散之间的绝缘层与金属通孔连接到接合焊盘金属。 N +扩散与P +扩散相邻。 N +扩散围绕N +和P +扩散，并将N +扩散结合在一起，以便在每个P +扩散周围完全形成连续的N +扩散。 N阱基本上位于N +和P +扩散之下。 周围的N +扩散与其下面的N阱的边缘部分重叠。 N +扩散的外部部分，与N阱重叠的部分在P-阱内。 P-阱可以是集成电路的衬底。 另外N +扩散围绕围绕P +扩散的N +扩散。 另一个N +扩散在P-阱中，场氧化物可以位于N +扩散与另一个N +扩散之间。 形成NPN场晶体管，其中N +扩散为晶体管集电极，P阱为晶体管基极，另一N +扩散为发射极。 另一个N +扩散（发射极）可以通过导电连接（例如金属或低电阻半导体材料）连接到地。

公开(公告)号：US5870409A

公开(公告)日：1999-02-09

申请号：US671011

申请日：1996-06-28

Applicant: Randy Yach ,  Rodney Drake

Inventor： Randy Yach ,  Rodney Drake

IPC: G01R31/00 ,  G02F1/13 ,  G02F1/133 ,  G06F11/267 ,  G09G3/00 ,  G09G3/36 ,  H04N5/66 ,  G01R31/28

CPC classification number: G09G3/006 ,  G06F11/2221

Abstract: A method is disclosed for testing a high speed microcontroller fabricated on a semiconductor chip, and for testing relatively low speed functions of a liquid crystal display (LCD) module on the chip that drives an off-chip LCD for an external system to be controlled by the microcontroller with a plurality of discrete analog voltage levels for performing the LCD functions. Digital values are multiplexed in time slots of a test waveform to simulate in high speed digital format of a test mode the low speed timing, relative magnitude and functionality of analog voltage levels used to drive the LCD; A high speed driver is selectively coupled to a pin of the chip, to which the discrete analog voltage levels are normally applied at low speed to drive the LCD, and the test waveform is applied to the high speed driver. The digital values and timing that appear on the pin are then monitored as an indication of proper functionality of the LCD module. The high speed driver is switched out and the normal low speed LCD driver is switched back for return to an LCD user mode when the test mode is completed. Monitoring the pin with a digital tester allows verification that pin pulses in predetermined time slots indicate the corresponding analog voltage level is being applied at the proper time during normal operation of the LCD module, and digitally testing of continuity in an analog channel. A transistor normally employed on the chip for electrostatic discharge protection is activated to selectively couple the high speed driver to the pin for the high speed testing mode.

Abstract translation: 公开了一种用于测试在半导体芯片上制造的高速微控制器的方法，并且用于测试芯片上的液晶显示器（LCD）模块的相对低速功能，该芯片驱动用于外部系统的片外LCD以由 具有用于执行LCD功能的多个离散模拟电压电平的微控制器。 数字值在测试波形的时隙中进行多路复用，以模拟用于驱动LCD的模拟电压电平的低速定时，相对幅度和功能的测试模式的高速数字格式; 选择性地将高速驱动器耦合到芯片的引脚，通过低速驱动分立的模拟电压电平来驱动LCD，测试波形被施加到高速驱动器。 然后监视引脚上出现的数字值和时序作为LCD模块正常功能的指示。 当测试模式完成时，高速驱动器被切换并且正常的低速LCD驱动器被切回以返回到LCD用户模式。 使用数字测试仪监控引脚，可以验证在预定时隙内的引脚脉冲表示在LCD模块正常工作期间的适当时间正在施加相应的模拟电压电平，并对模拟通道的连续性进行数字测试。 通常在芯片上用于静电放电保护的晶体管被​​激活以选择性地将高速驱动器耦合到用于高速测试模式的引脚。

公开(公告)号：US07919973B2

公开(公告)日：2011-04-05

申请号：US12128403

申请日：2008-05-28

Applicant: Randy Yach ,  Tommy Stevens

Inventor： Randy Yach ,  Tommy Stevens

IPC: G01R31/00 ,  G01R31/26

CPC classification number: G01R31/31717 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318511 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.

Abstract translation: 用于监测半导体制造工艺的方法产生半导体芯片晶片。 每个芯片都有一个或多个二极管。 每个二极管可寻址作为阵列的一部分，对应于芯片的物理位置，并且串联连接到堆叠。 堆叠由一个更多的垂直互连和金属触点组成。 寻址二极管和相关联的垂直互连堆栈，并测量通过阵列中的每个垂直互连堆叠的电流。

公开(公告)号：US07203818B2

公开(公告)日：2007-04-10

申请号：US10796771

申请日：2004-03-09

Applicant: Edward Brian Boles ,  Rodney Jay Drake ,  Darrel Ray Johansen ,  Sumit K. Mitra ,  Randy Yach ,  James Grosbach ,  Joshua M. Conner ,  Joseph W. Triece

Inventor： Edward Brian Boles ,  Rodney Jay Drake ,  Darrel Ray Johansen ,  Sumit K. Mitra ,  Randy Yach ,  James Grosbach ,  Joshua M. Conner ,  Joseph W. Triece

IPC: G06F12/00 ,  G06F15/00

CPC classification number: G06F9/30192 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/325

Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.

Abstract translation: 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。 正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此，两个文件寄存器用于一些两个操作数指令。 这允许在两个寄存器之间直接移动数据，而不经过W寄存器。 因此，提高性能并减少程序内存使用。

公开(公告)号：US20050247980A1

公开(公告)日：2005-11-10

申请号：US11183640

申请日：2005-07-18

Applicant: Randy Yach ,  Gregg Dix

Inventor： Randy Yach ,  Gregg Dix

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L27/0259

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

公开(公告)号：US06708268B1

公开(公告)日：2004-03-16

申请号：US09280112

申请日：1999-03-26

Applicant: Edward Brian Boles ,  Rodney Drake ,  Darrel Johansen ,  Sumit Mitra ,  Joseph Triece ,  Randy Yach

Inventor： Edward Brian Boles ,  Rodney Drake ,  Darrel Johansen ,  Sumit Mitra ,  Joseph Triece ,  Randy Yach

IPC: G06F1208

CPC classification number: G06F9/30192 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/325

Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.

Abstract translation: 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。 正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此，在两个操作数指令中要使用两个文件寄存器。 这允许在两个寄存器之间直接移动数据，而不经过W寄存器。 从而提高性能并减少程序内存的使用。

公开(公告)号：US08164416B2

公开(公告)日：2012-04-24

申请号：US12490545

申请日：2009-06-24

Applicant: Thomas Youbok Lee ,  James B. Nolan ,  Steve Vernier ,  Randy Yach ,  Alan Lamphier

Inventor： Thomas Youbok Lee ,  James B. Nolan ,  Steve Vernier ,  Randy Yach ,  Alan Lamphier

IPC: G05B19/00

CPC classification number: H04B1/1615 ,  B60R25/24 ,  G06K19/07 ,  G07C9/00309 ,  G07C2009/00333 ,  G07C2009/00373 ,  G07C2009/00769 ,  H04W52/0225 ,  Y02D70/166 ,  Y02D70/40

Abstract: A remote keyless entry (RKE) transponder has a programmable selective wake-up filter for determining whether the RKE transponder should wake-up to process a received signal. The wake-up filter correlates the timing of an input signal's carrier amplitude on and off time periods to a predefined programmable time period profile for a desired signal which has a certain carrier on time (time period on) and a certain carrier off time (time period off) arranged into a coded “header.” When a received signal matches the predefined time period profile, then the RKE transponder will wake-up to process the incoming signal data. The predefined time period profile may be programmable and may be stored in a header configuration register. Each RKE transponder has unique predefined time period on and time period off profiles.

Abstract translation: 远程无钥匙进入（RKE）转发器具有可编程选择性唤醒滤波器，用于确定RKE应答器是否应该被唤醒以处理接收到的信号。 唤醒滤波器将输入信号的载波幅度开和关时间周期的定时与预定的可编程时间段分布相关联，用于对于具有一定载波的时间（时间周期）和某个载波关闭时间（时间周期）的期望信号 周期关闭），当接收到的信号与预定义的时间段配置文件匹配时，RKE应答器将被唤醒以处理输入的信号数据。 预定义的时间段简档可以是可编程的，并且可以存储在头部配置寄存器中。 每个RKE转发器具有独特的预定义时间段和时间段关闭配置文件。

公开(公告)号：US08072233B2

公开(公告)日：2011-12-06

申请号：US13033792

申请日：2011-02-24

Applicant: Randy Yach ,  Tommy Stevens

Inventor： Randy Yach ,  Tommy Stevens

IPC: G01R31/00 ,  G01R31/26

CPC classification number: G01R31/31717 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318511 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.

公开(公告)号：US20110140728A1

公开(公告)日：2011-06-16

申请号：US13033792

申请日：2011-02-24

Applicant: Randy Yach ,  Tommy Stevens

Inventor： Randy Yach ,  Tommy Stevens

IPC: G01R31/26

CPC classification number: G01R31/31717 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318511 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.

Abstract translation: 用于监测半导体制造工艺的方法产生半导体芯片晶片。 每个芯片都有一个或多个二极管。 每个二极管可寻址作为阵列的一部分，对应于芯片的物理位置，并且串联连接到堆叠。 堆叠由一个更多的垂直互连和金属触点组成。 寻址二极管和相关联的垂直互连堆栈，并测量通过阵列中的每个垂直互连堆叠的电流。

公开(公告)号：US20100148700A1

公开(公告)日：2010-06-17

申请号：US12622745

申请日：2009-11-20

Applicant: Ward R. Brown ,  Randy Yach

Inventor： Ward R. Brown ,  Randy Yach

IPC: H05B37/02 ,  G05B24/02

CPC classification number: H05B33/0806 ,  H05B33/0815

Abstract: A constant current output sink or source eliminates a current limiting series resistor for a light emitting diode (LED) and maintains a constant light intensity from the LED for all operating and manufacturing variables of a digital device since the current through the LED is maintained at a constant value. The constant current output sink or source may be programmable for selection of a constant current value from a plurality of constant current values available.

Abstract translation: 恒定电流输出接收器或源极消除了用于发光二极管（LED）的限流串联电阻器，并且为了数字器件的所有操作和制造变量而保持来自LED的恒定的光强度，因为通过LED的电流维持在 恒定值。 恒流输出接收器或源可以是可编程的，用于从可用的多个恒定电流值中选择恒定电流值。