公开(公告)号：US07475399B2

公开(公告)日：2009-01-06

申请号：US10755877

申请日：2004-01-13

Applicant: Ravi Kumar Arimilli ,  Randal Craig Swanberg

Inventor： Ravi Kumar Arimilli ,  Randal Craig Swanberg

IPC: G06F9/46 ,  G06F9/30

CPC classification number: G06F11/3466 ,  G06F2201/88

Abstract: According to a method of operating a data processing system, one or more monitoring parameter sets are established in a processing unit within the data processing system. The processing unit monitors, in hardware, execution of each of a plurality of schedulable software entities within the processing unit in accordance with a monitoring parameter set among the one or more monitoring parameter sets. The processing unit then reports to software executing in the data processing system utilization of hardware resources by each of the plurality of schedulable software entities. The hardware utilization information reported by the processing unit may be stored and utilized by software to schedulable execution of the schedulable software entities reported by the processing unit. The hardware utilization information may also be utilized to generate a classification of at least one executing schedulable software entity, which may be communicated to the processing unit to dynamically modify an allocation of hardware resources to the schedulable software entity.

Abstract translation: 根据操作数据处理系统的方法，在数据处理系统内的处理单元中建立一个或多个监视参数组。 处理单元根据在一个或多个监视参数组中设置的监视参数，硬件地监视处理单元内的多个可调度软件实体中的每一个的执行。 然后，处理单元通过多个可调度软件实体中的每一个向硬件资源的数据处理系统利用执行的软件报告。 由处理单元报告的硬件利用信息可由软件存储和利用，以便可处理单元报告的可调度软件实体的可调度执行。 还可以利用硬件利用信息来生成至少一个执行的可调度软件实体的分类，所述可执行可调度软件实体可以被传送到处理单元以动态地修改对可调度软件实体的硬件资源的分配。

公开(公告)号：US07356568B2

公开(公告)日：2008-04-08

申请号：US10318514

申请日：2002-12-12

Applicant: Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

Inventor： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

IPC: G06F13/00

CPC classification number: G06F9/30101

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract translation: 包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。 每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率 无限流的加载，存储和无效命令。

公开(公告)号：US07039832B2

公开(公告)日：2006-05-02

申请号：US10313329

申请日：2002-12-05

Applicant: Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

Inventor： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

IPC: G06F11/00

CPC classification number: G06F11/2236

Abstract: A method and system are disclosed for running a manufacturing-level test program on an installed processor by interrupting processor execution of a non-test process. Periodic execution of the manufacturing-level test program allows the processor to continually self-test during normal function operation, in order to facilitate proper maintenance and function of the processor and a data processing system of which the processor is a part.

Abstract translation: 公开了一种方法和系统，用于通过中断非测试过程的处理器执行来在安装的处理器上运行制造级测试程序。 制造级测试程序的定期执行允许处理器在正常功能操作期间不间断地进行自检，以便促进处理器和处理器作为其一部分的数据处理系统的适当维护和功能。

公开(公告)号：US07017031B2

公开(公告)日：2006-03-21

申请号：US10268740

申请日：2002-10-10

Applicant: Ravi Kumar Arimilli ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Derek Edward Williams

IPC: G06F9/30

CPC classification number: G06F12/0815 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F12/0811

Abstract: A data processing system includes a global promotion facility containing a plurality of promotion bit fields, an interconnect, and a plurality of processing units coupled to the global promotion facility and to the interconnect. A first processing unit includes an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a particular promotion bit field within the global promotion facility, and a promotion awareness facility. In response to the first processing unit snooping a request by a second processing unit for the particular promotion bit field, the first processing unit records an association between the second processing unit and the particular promotion bit field in the global promotion facility. After the request and release of the particular promotion bit field by the first processing unit, the first processing unit checks the promotion awareness facility for an association for the particular promotion bit and responsive to the checking, pushes the particular promotion bit field to the second processing unit utilizing an unsolicited operation on the interconnect such that no additional request by the second processing unit is required.

Abstract translation: 数据处理系统包括包含多个升级位字段的全球推广设施，互连以及耦合到全球促销设施和互连的多个处理单元。 第一处理单元包括指令排序单元，执行单元，执行获取指令以获取全球促销设施内的特定促销位字段，以及促销意识设施。 响应于第一处理单元窥探特定促销位字段的第二处理单元的请求，第一处理单元在全局推广设备中记录第二处理单元和特定促销位字段之间的关联。 在由第一处理单元请求和释放特定促销位字段之后，第一处理单元检查促销感知设施以获得针对特定促销位的关联并且响应于检查，将特定促销位字段推送到第二处理 在所述互连上使用非请求操作的单元，使得不需要所述第二处理单元的附加请求。

公开(公告)号：US06970976B1

公开(公告)日：2005-11-29

申请号：US09340074

申请日：1999-06-25

Applicant: Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie

Inventor： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/14

CPC classification number: G06F12/0897 ,  G06F12/0831 ,  G06F12/0859 ,  G06F12/1027

Abstract: A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (Li) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.

Abstract translation: 一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。 将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。 使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。 然后可能不精确地重新加载上层（Li）高速缓存（上级缓存也可能不精确地用存储指令重新加载）。 低级（L​​2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（ 基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。 本发明可以应用于例如指令，操作数数据和翻译高速缓存。

公开(公告)号：US06963967B1

公开(公告)日：2005-11-08

申请号：US09588508

申请日：2000-06-06

Applicant: Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

Inventor： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861

Abstract: Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier operation are created. The barrier operation is placed on an interconnect after the memory access request is issued to a memory system. After the barrier operation has completed, the memory access request is completed in program order. When the memory access request is a load request, the load request is speculatively issued if a barrier operation is pending. Data returned by the speculatively issued load request is only returned to a register or execution unit of the processor when an acknowledgment is received for the barrier operation.

Abstract translation: 公开了一种在数据处理系统中处理指令的方法。 包括存储器访问指令的指令序列以处理器的顺序被接收。 响应于接收到存储器访问指令，创建存储器访问请求和屏障操作。 在将存储器访问请求发布到存储器系统之后，屏障操作被放置在互连上。 屏障操作完成后，按程序顺序完成内存访问请求。 当存储器访问请求是加载请求时，如果屏障操作正在等待，则推测性地发出加载请求。 当接收到用于屏障操作的确认时，由推测发出的加载请求返回的数据仅返回到处理器的寄存器或执行单元。

公开(公告)号：US06928524B2

公开(公告)日：2005-08-09

申请号：US10313328

申请日：2002-12-05

Applicant: Ravi Kumar Arimilli ,  Benjiman Lee Goodman ,  Jody Bern Joyner

Inventor： Ravi Kumar Arimilli ,  Benjiman Lee Goodman ,  Jody Bern Joyner

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0831

Abstract: A method for reserving memory buffers for receiving data prior to the actual movement of data on a data processing system. A naked write operation is generated that includes a destination address and an address of the processor generating the write operation. The naked write operation is then issued on the fabric of said data processing system without any accompanying data. The naked write operation is snooped by the memory controller associated with the destination address. The memory controller then provides a response that is sent to the processor. The response sent depends on whether the memory controller is able to allocate a buffer to the naked write operation. When the memory controller is able to allocate a buffer to the naked write operation, the memory controller issues a Null response, which triggers a read operation that sends the corresponding data to the buffer at a later time.

Abstract translation: 一种用于在数据处理系统上实际数据移动之前预留用于接收数据的存储器缓冲器的方法。 生成包含目的地地址和生成写入操作的处理器的地址的裸写操作。 然后在所述数据处理系统的结构上发出裸体写入操作，而没有任何伴随的数据。 裸机写操作由与目标地址相关联的存储器控​​制器进行窥探。 然后，存储器控制器提供发送到处理器的响应。 发送的响应取决于内存控制器是否能够为裸写操作分配缓冲区。 当存储器控制器能够为裸写操作分配缓冲器时，存储器控制器发出Null响应，该响应触发稍后将相应数据发送到缓冲器的读取操作。

公开(公告)号：US06920521B2

公开(公告)日：2005-07-19

申请号：US10268741

申请日：2002-10-10

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Sanjeev Ghai ,  Kenneth Lee Wright

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Sanjeev Ghai ,  Kenneth Lee Wright

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08

CPC classification number: G06F12/0292 ,  G06F12/0646

Abstract: A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the operating system stalls. Write memory requests addressed to the real address space currently associated with the sourcing memory module indicated by either the FROM or TO real address space. As will be appreciated, a memory module can be inserted, removed or replaced in physical memory without the operating system having to stop all memory operations in the memory to accomplish the physical memory change.

Abstract translation: 移动引擎和操作系统透明地重新配置物理内存以实现内存模块的加法，减法或更换。 操作系统将FROM和TO存储在存储器中的唯一字段中存储，用于虚拟化正在重新配置的存储器模块的物理地址，并通过使用硬件功能而不是软件来实时提供重新配置。 使用FROM和TO实地址选择源和目标，移动引擎将要删除或重新配置的内存模块的内容复制到剩余或插入的内存模块中。 然后，将与重新配置的存储器模块相关联的真实地址重新分配给接收复制内容的存储器模块，从而由操作系统利用的可寻址实地址空间创建虚拟物理映射到虚拟物理地址空间。 在移动存储器内容的过程中，操作系统停顿。 将存储器请求写入到由FROM或TO实地址空间指示的当前与源存储器模块相关联的实际地址空间。 如将理解的，可以在物理存储器中插入，移除或替换存储器模块，而不需要操作系统停止存储器中的所有存储器操作来完成物理存储器改变。

公开(公告)号：US06886079B2

公开(公告)日：2005-04-26

申请号：US09885998

申请日：2001-06-21

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr.

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr.

IPC: G06F9/52 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0817 ,  G06F12/0813

Abstract: A non-uniform memory access (NUMA) computer system includes at least one remote node and a home node coupled by a node interconnect. The home node contains a home system memory and a memory controller. In response to receipt of a data request from a remote node, the memory controller determines whether to grant exclusive or non-exclusive ownership of requested data specified in the data request by reference to history information indicative of prior data accesses originating in the remote node. The memory controller then transmits the requested data and an indication of exclusive or non-exclusive ownership to the remote node.

Abstract translation: 非均匀存储器访问（NUMA）计算机系统包括至少一个远程节点和通过节点互连耦合的家庭节点。 家庭节点包含家庭系统存储器和存储器控制器。 响应于从远程节点接收到数据请求，存储器控制器通过参考指示源自远程节点的先前数据访问的历史信息来确定是否授予在数据请求中指定的所请求数据的排他或非排他所有权。 然后，存储器控制器将所请求的数据和独占或非排他所有权的指示发送到远程节点。

公开(公告)号：US06865695B2

公开(公告)日：2005-03-08

申请号：US09915668

申请日：2001-07-26

Applicant: Jody Bern Joyner ,  Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung

Inventor： Jody Bern Joyner ,  Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung

IPC: G06F11/00 ,  G06F11/20

CPC classification number: G06F11/2007

Abstract: A computer system of a number of processing nodes operate either in a loop configuration or off of a common bus with high speed, high performance wide bandwidth characteristics. The processing nodes in the system are also interconnected by a separate narrow bandwidth, low frequency recovery bus. When problems arise with node operations on the high speed bus, operations are transferred to the low frequency recovery bus and continue there at a slower rate for recovery operations. The recovery technique may be used to increase system speed and performance on a dynamic basis.

Abstract translation: 多个处理节点的计算机系统以具有高速，高性能宽带宽特性的公共总线的环路配置或关闭操作。 系统中的处理节点也通过单独的窄带宽，低频恢复总线互连。 当高速总线上的节点操作出现问题时，操作将传输到低频恢复总线，并以较慢的速率继续进行恢复操作。 恢复技术可以用于在动态基础上提高系统速度和性能。