公开(公告)号：US20220223464A1

公开(公告)日：2022-07-14

申请号：US17547829

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US12272592B2

公开(公告)日：2025-04-08

申请号：US18664656

申请日：2024-05-15

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H10D30/65 ,  H10D62/10 ,  H10D64/27

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US12250834B2

公开(公告)日：2025-03-11

申请号：US17737231

申请日：2022-05-05

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L21/765 ,  H10D30/01 ,  H10D30/65 ,  H10D62/17 ,  H10D64/00 ,  H10D84/00

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

公开(公告)号：US12107160B2

公开(公告)日：2024-10-01

申请号：US17726515

申请日：2022-04-21

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng ,  Chien-Wei Chiu

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76202 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66681

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

公开(公告)号：US20230253494A1

公开(公告)日：2023-08-10

申请号：US17847053

申请日：2022-06-22

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Yu-Ting Yeh ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/66681

Abstract: A high voltage device includes: a semiconductor layer, a well, a drift oxide region, a body region, a gate, a source, a drain, and a field plate. The well has a first conductivity type, and is formed in a semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type, and is formed in the semiconductor layer, wherein the body region and a drift region are connected in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer, wherein the source and the drain are in the body region and the well, respectively. The field plate is formed on and connected with the drift oxide region, wherein the field plate is electrically conductive and has a temperature coefficient (TC) not higher than 4 ohm/° C.

公开(公告)号：US20230046174A1

公开(公告)日：2023-02-16

申请号：US17737231

申请日：2022-05-05

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L21/765 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

公开(公告)号：US20220376110A1

公开(公告)日：2022-11-24

申请号：US17726515

申请日：2022-04-21

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng ,  Chien-Wei Chiu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

公开(公告)号：US20220238727A1

公开(公告)日：2022-07-28

申请号：US17571401

申请日：2022-01-07

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H01L29/866 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region.

公开(公告)号：US20240105844A1

公开(公告)日：2024-03-28

申请号：US18462803

申请日：2023-09-07

Applicant: Richtek Technology Corporation

Inventor： Ying-Shiou Lin ,  Wu-Te Weng ,  Yong-Zhong Hu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L29/66492

Abstract: A native NMOS device includes: a P-type epitaxial layer, a first and a second insulation region, a first P-type well, a second P-type well, a gate, an N-type source, and an N-type drain. The P-type epitaxial layer has a first concentration of P-type doped impurities. The first P-type well completely encompasses and is in contact with a lower surface of the N-type source. The second P-type well completely encompasses and is in contact with a lower surface of the N-type drain. Each of the first P-type well and the second P-type well has a second concentration of P-type doped impurities, and the second concentration of P-type doped impurities is higher than the first concentration of P-type doped impurities. The second concentration of P-type doped impurities is sufficient for preventing a leakage current from flowing between the N-type drain and the P-type substrate while the native NMOS device is in operation.

公开(公告)号：US20230178648A1

公开(公告)日：2023-06-08

申请号：US17983434

申请日：2022-11-09

Applicant: Richtek Technology Corporation

Inventor： Chih-Wen Hsiung ,  Wu-Te Weng ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/42368 ,  H01L29/7835 ,  H01L29/66659 ,  H01L29/1095

Abstract: An NMOS half-bridge power device includes: a semiconductor layer, a plurality of insulation regions, a first N-type high voltage well and a second N-type high voltage well, which are formed by one same ion implantation process, a first P-type high voltage well and a second P-type high voltage well, which are formed by one same ion implantation process, a first drift oxide region and a second drift oxide region, which are formed by one same etch process including etching a drift oxide layer; a first gate and a second gate, which are formed by one same etch process including etching a poly silicon layer, a first P-type body region and a second P-type body region, which are formed by one same ion implantation process, a first N-type source and a first N-type drain, and a second N-type source and a second N-type drain.