公开(公告)号：US20230131821A1

公开(公告)日：2023-04-27

申请号：US17858117

申请日：2022-07-06

Applicant: Richtek Technology Corporation

Inventor： Heng-Chi Huang ,  Sheng-Yao Wu ,  Chi-Yung Wu ,  Yong-Zhong Hu

IPC: H01L23/495

Abstract: A heat dissipation structure, includes: a lead frame, including a high temperature pad and a low temperature pad, the high temperature pad and the low temperature pad being two portions in the lead frame which are separated from each other, wherein a high heat generation component is disposed on the high temperature pad; and a high thermal conduction element, including two sides which are respectively directly connected with the high temperature pad and the low temperature pad, to dissipate the heat energy from the high heat generation component to the low temperature pad.

公开(公告)号：US11522536B2

公开(公告)日：2022-12-06

申请号：US17568637

申请日：2022-01-04

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

公开(公告)号：US20220157622A1

公开(公告)日：2022-05-19

申请号：US17485339

申请日：2021-09-25

Applicant: Richtek Technology Corporation

Inventor： Heng-Chi Huang ,  Yong-Zhong Hu ,  Hao-Lin Yen

IPC: H01L21/48 ,  H01L21/683 ,  H01L21/78 ,  H01L23/373

Abstract: A chip packaging method includes: providing plural chip units; providing a base material, and placing the chip units on the base material; providing an adhesive layer to adhere a metal foil to the chip unit, wherein the metal foil is a part of the base material or additional to the base material; and cutting the chip units on the base material to form plural separated chip package units, wherein each of the chip package units includes a cut metal foil part.

公开(公告)号：US20240234264A1

公开(公告)日：2024-07-11

申请号：US18616275

申请日：2024-03-26

Applicant: Richtek Technology Corporation

Inventor： Hao-Lin Yen ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952

Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

公开(公告)号：US20230098393A1

公开(公告)日：2023-03-30

申请号：US17847231

申请日：2022-06-23

Applicant: Richtek Technology Corporation

Inventor： Hao-Lin Yen ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A lead frame includes: at least one ductile structure, including a bond area, a die paddle, or a lead finger; and at least one sacrificial structure, connected between a corresponding ductile structure and a corresponding near portion in the lead frame, wherein the near portion is a portion of the lead frame close to the ductile structure.

公开(公告)号：US20220208628A1

公开(公告)日：2022-06-30

申请号：US17565402

申请日：2021-12-29

Applicant: Richtek Technology Corporation

Inventor： Shih-Chieh Lin ,  Yong-Zhong Hu ,  Heng-Chi Huang ,  Hao-Lin Yen

IPC: H01L23/31 ,  H01L23/15 ,  H01L23/495 ,  H01L23/367

Abstract: A chip packaging structure includes: at least one semiconductor chip, having a signal processing function; a base material, wherein the semiconductor chip is disposed on the base material; at least one thermal conduction plate, disposed on the base material; and a package material, encapsulating the base material, the thermal conduction plate, and the semiconductor chip. The thermal conduction plate forms at least one thermal conduction channel in the package material.

公开(公告)号：US20220181238A1

公开(公告)日：2022-06-09

申请号：US17490038

申请日：2021-09-30

Applicant: Richtek Technology Corporation

Inventor： Hao-Lin Yen ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

公开(公告)号：US20250142873A1

公开(公告)日：2025-05-01

申请号：US18435550

申请日：2024-02-07

Applicant: Richtek Technology Corporation

Inventor： Wu-Te Weng ,  Yi-Rong Tu ,  Ying-Shiou Lin ,  Yong-Zhong Hu

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/40 ,  H01L29/66

Abstract: A depletion type vertical discrete NMOS device includes: an N-type epitaxial layer formed on an N-type substrate, wherein the N-type epitaxial layer has a top surface and a bottom surface opposite to each other; a P-type well formed in the N-type epitaxial layer; a gate formed outside and connected with the N-type epitaxial layer; an N-type source formed in the N-type epitaxial layer and in contact with the P-type well; an N-type drain including a part of the N-type substrate, which is formed outside and under the N-type epitaxial layer; and an N-type region formed and connected between the P-type well and the gate, which provides a channel, such that the N-type source and the N-type drain are electrically connected with each other during conduction operation, whereas, the N-type source and the N-type drain are electrically disconnected from each other during non-conduction operation.

公开(公告)号：US20240297067A1

公开(公告)日：2024-09-05

申请号：US18664656

申请日：2024-05-15

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/7621 ,  H01L21/76221 ,  H01L21/76281 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US12062570B2

公开(公告)日：2024-08-13

申请号：US17547829

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/7621 ,  H01L21/76221 ,  H01L21/76281 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.