公开(公告)号：US07127697B1

公开(公告)日：2006-10-24

申请号：US10631461

申请日：2003-07-30

申请人： Robert W. Wells ,  Robert D. Patrie ,  Andrew J. DeBaets

发明人： Robert W. Wells ,  Robert D. Patrie ,  Andrew J. DeBaets

IPC分类号： G06F17/50

CPC分类号： G01R31/318516

摘要： Methods of utilizing partially defective PLDs, i.e., PLDs having localized defects. A partially defective PLD is tested for compatibility with a particular configuration bitstream. If the partially defective PLD is compatible with the bitstream (i.e., if the localized defect has no effect on the functionality of the design implemented by the bitstream), a product is made available that includes both the bitstream and the partially defective PLD. In some embodiments, the bitstream is stored in a memory device such as a programmable read-only memory (PROM). In some embodiments, the product is a chip set that includes the partially defective PLD and a separately-packaged PROM in which the bitstream has previously been stored. In some embodiments, the PROM is manufactured as part of the FPGA die.

摘要翻译： 利用部分有缺陷的PLD的方法，即具有局部缺陷的PLD。 测试部分有缺陷的PLD与特定配置比特流的兼容性。 如果部分有缺陷的PLD与比特流兼容（即，如果局部缺陷对由比特流实现的设计的功能没有影响），则产生包括比特流和部分缺陷的PLD的产品。 在一些实施例中，比特流存储在诸如可编程只读存储器（PROM）的存储器件中。 在一些实施例中，产品是包括部分有缺陷的PLD的芯片组和其中预先存储了比特流的单独封装的PROM。 在一些实施例中，PROM被制造为FPGA管芯的一部分。

公开(公告)号：US06817006B1

公开(公告)日：2004-11-09

申请号：US10104324

申请日：2002-03-22

申请人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

发明人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

IPC分类号： G06F1750

CPC分类号： G01R31/318519

摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。

公开(公告)号：US07007250B1

公开(公告)日：2006-02-28

申请号：US10388000

申请日：2003-03-12

申请人： Shekhar Bapat ,  Robert W. Wells ,  Robert D. Patrie ,  Andrew W. Lai

发明人： Shekhar Bapat ,  Robert W. Wells ,  Robert D. Patrie ,  Andrew W. Lai

IPC分类号： G06F17/50

CPC分类号： G01R31/318519 ,  G06F17/5054

摘要： Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.

摘要翻译： 公开的利用包含至少一个局部缺陷的可编程逻辑器件的方法。 测试这些设备以确定其适用于实施可能不需要受缺陷影响的资源的所选客户设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对于给定客户设计的适用性，而不要求供应商了解设计。

公开(公告)号：US06651238B1

公开(公告)日：2003-11-18

申请号：US09837380

申请日：2001-04-17

申请人： Robert W. Wells ,  Robert D. Patrie ,  Eric J. Thorne ,  Michael M. Matera

发明人： Robert W. Wells ,  Robert D. Patrie ,  Eric J. Thorne ,  Michael M. Matera

IPC分类号： G06F1750

CPC分类号： G01R31/318519 ,  G01R31/2853 ,  G01R31/318342

摘要： Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.

摘要翻译： 提供了可编程逻辑器件（PLD）的可编程互连的故障覆盖。 用户的设计被建模，从而确定设备中的可编程互连路径。 然后修改用户的逻辑设计，从而有助于检测故障。 具体地说，PLD中的任何函数发生器被实现为预定的逻辑门，从而形成逻辑门树设计。 如果需要，用户设计中的同步元素将被保留和转换，以提供可控性。 然后，可以在新设计中行使矢量。 可以将PLD的第一次回读与设计的无故障模型的第二次回读进行比较。

公开(公告)号：US06594797B1

公开(公告)日：2003-07-15

申请号：US09521947

申请日：2000-03-09

申请人： Rick W. Dudley ,  Jae Cho ,  Robert D. Patrie ,  Robert W. Wells

发明人： Rick W. Dudley ,  Jae Cho ,  Robert D. Patrie ,  Robert W. Wells

IPC分类号： G06F1100

CPC分类号： G01R31/31937 ,  G01R31/318516 ,  G01R31/3191

摘要： Described are methods and circuits for accurately placing signal transitions, or “edges,” simultaneously on two or more pins of an integrated circuit (IC). A conventional tester is connected to an integrated circuit, such as a programmable logic device. The integrated circuit is adapted to include a coincidence detector that compares the timing of edges on two input pins of the integrated circuit. The coincidence detector indicates when the two edges are coincident, allowing an operator of the tester to adjust the tester to establish coincidence. The amount of offset necessary to provide coincident edges is stored in a database for later use in deskewing edges used in subsequent tests. The integrated circuit can be a programmable logic device configured to include one or more coincidence detectors with which to place edges relative to one another on different pins.

摘要翻译： 描述了用于在集成电路（IC）的两个或更多个引脚上同时精确地放置信号转换或“边沿”的方法和电路。 常规的测试器连接到诸如可编程逻辑器件的集成电路。 集成电路适于包括比较集成电路的两个输入引脚上的边沿的定时的重合检测器。 重合检测器指示两个边缘何时重合，允许测试仪的操作者调整测试仪以建立巧合。 提供重合边缘所需的偏移量存储在数据库中，以供以后用于后续测试中使用的偏移校正边缘。 集成电路可以是可编程逻辑器件，其被配置为包括一个或多个重合检测器，用于在不同的引脚上相对于彼此放置边缘。

公开(公告)号：US06594610B1

公开(公告)日：2003-07-15

申请号：US09853351

申请日：2001-05-11

申请人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

发明人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

IPC分类号： G06F1900

CPC分类号： G01R31/318519 ,  G01R31/318342

摘要： A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

摘要翻译： 新的测试方法使用现场可编程门阵列来模拟故障，而不是使用单独的计算机来模拟故障。 在一个实施例中，选择几个（例如，两个或三个）已知的良好FPGA。 在FPGA配置的设计中引入了一个故障。 将配置加载到FPGA中。 应用测试向量并评估结果。 如果结果与无故障配置的结果不同，则会发现故障。 这种方法的一个应用是评估故障覆盖。 公开了可用于本发明的故障模型。

公开(公告)号：US06539508B1

公开(公告)日：2003-03-25

申请号：US09526138

申请日：2000-03-15

申请人： Robert D. Patrie ,  Robert W. Wells

发明人： Robert D. Patrie ,  Robert W. Wells

IPC分类号： H04B1700

CPC分类号： G01R31/318516

摘要： Described is a test circuit that can be instantiated on a programmable logic device to perform at-speed functional tests of programmable resources, including internal memory and routing resources. The resources to be tested are configured to instantiate a counter circuit connected to the address terminals of a linear-feedback shift register (LFSR). LFSRs are cyclic, in the sense that when clocked repeatedly they go through a fixed sequence of states. Consequently, an LFSR that starts with a known set of data has a predictable set of data after a given number of clock periods. The LFSR is preset to a known count and clocked a known number of times. The resulting count is then compared with a reference. If the resulting count matches the reference, then all of the resources used to implement the test circuit, including the memory and routing resources used to implement the LFSR, are deemed fully functional at the selected clock speed. A test circuit employing an LFSR can be duplicated many times on a given device under test to consume (and therefore test) as many resources as possible.

摘要翻译： 描述了可以在可编程逻辑器件上实例化的测试电路，以执行包括内部存储器和路由资源在内的可编程资源的高速功能测试。 要测试的资源被配置为实例化连接到线性反馈移位寄存器（LFSR）的地址端子的计数器电路。 在这种意义上，当重复时钟时，LFSR是循环的，它们经历固定的状态序列。 因此，以已知数据集开始的LFSR在给定数量的时钟周期之后具有可预测的数据集合。 LFSR预设为已知的计数，并且已知次数。 然后将得到的计数与参考值进行比较。 如果结果计数与引用匹配，则用于实现测试电路的所有资源（包括用于实现LFSR的存储器和路由资源）被视为在所选择的时钟速度下完全正常工作。 使用LFSR的测试电路可以在给定的被测设备上重复许多次以消耗尽可能多的资源（并因此测试）。