公开(公告)号：US06594610B1

公开(公告)日：2003-07-15

申请号：US09853351

申请日：2001-05-11

申请人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

发明人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

IPC分类号： G06F1900

CPC分类号： G01R31/318519 ,  G01R31/318342

摘要： A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

摘要翻译： 新的测试方法使用现场可编程门阵列来模拟故障，而不是使用单独的计算机来模拟故障。 在一个实施例中，选择几个（例如，两个或三个）已知的良好FPGA。 在FPGA配置的设计中引入了一个故障。 将配置加载到FPGA中。 应用测试向量并评估结果。 如果结果与无故障配置的结果不同，则会发现故障。 这种方法的一个应用是评估故障覆盖。 公开了可用于本发明的故障模型。

公开(公告)号：US06891395B2

公开(公告)日：2005-05-10

申请号：US10853981

申请日：2004-05-25

申请人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

发明人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F17/50 ,  H01L21/82 ,  H03K19/173

CPC分类号： G01R31/318519 ,  G06F17/5054

摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。

公开(公告)号：US06817006B1

公开(公告)日：2004-11-09

申请号：US10104324

申请日：2002-03-22

申请人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

发明人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

IPC分类号： G06F1750

CPC分类号： G01R31/318519

摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。

公开(公告)号：US07454675B1

公开(公告)日：2008-11-18

申请号：US10970936

申请日：2004-10-22

申请人： Robert W. Wells ,  Shekhar Bapat ,  Tassanee Payakapan ,  Shahin Toutounchi

发明人： Robert W. Wells ,  Shekhar Bapat ,  Tassanee Payakapan ,  Shahin Toutounchi

IPC分类号： G01R31/28

CPC分类号： G01R31/318519 ,  G01R31/31707

摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.

摘要翻译： 测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。 该方法通过向编程的电路提供测试输入来继续。 该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。 该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。 该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。

公开(公告)号：US06920621B1

公开(公告)日：2005-07-19

申请号：US10644158

申请日：2003-08-20

申请人： Shahin Toutounchi ,  Erik V. Chmelar ,  Robert W. Wells

发明人： Shahin Toutounchi ,  Erik V. Chmelar ,  Robert W. Wells

IPC分类号： G01R31/30 ,  G06F11/24 ,  G06F17/50

CPC分类号： G06F11/24 ,  G01R31/3008 ,  G06F17/5027

摘要： Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused interconnect lines, both used and unused interconnect lines are driven to a first logic level, and the leakage current is measured. The used interconnect lines are driven to a second logic level, while the unused lines remain at the first logic level. The current is again measured, and the difference between the two measurements is determined. If the difference exceeds a predetermined threshold, the device design combination is rejected. Some embodiments provide methods of testing for shorts between used and unused interconnect lines for a design targeted to a partially defective PLD.

摘要翻译： 测试集成电路中的互连线之间的短路（例如桥接缺陷）的方法。 例如，在可编程逻辑器件（PLD）中实现的设计中，使用一些互连线，而其他互连线未被使用。 为了测试使用和未使用的互连线之间的短路，使用的和未使用的互连线都被驱动到第一逻辑电平，并且测量泄漏电流。 所使用的互连线被驱动到第二逻辑电平，而未使用的线保持在第一逻辑电平。 再次测量电流，并确定两次测量之间的差异。 如果差异超过预定阈值，则设备组合被拒绝。 一些实施例提供了用于针对部分有缺陷的PLD的设计的在使用的和未使用的互连线之间的短路的测试方法。

公开(公告)号：US07725787B1

公开(公告)日：2010-05-25

申请号：US12235489

申请日：2008-09-22

申请人： Robert W. Wells ,  Shekhar Bapat ,  Tassanee Payakapan ,  Shahin Toutounchi

发明人： Robert W. Wells ,  Shekhar Bapat ,  Tassanee Payakapan ,  Shahin Toutounchi

IPC分类号： G01R31/28

CPC分类号： G01R31/318519 ,  G01R31/31707

摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.

摘要翻译： 测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。 该方法通过向编程的电路提供测试输入来继续。 该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。 该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。 该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。

公开(公告)号：US07917820B1

公开(公告)日：2011-03-29

申请号：US12123867

申请日：2008-05-20

申请人： Adarsh Pavle ,  Shahin Toutounchi

发明人： Adarsh Pavle ,  Shahin Toutounchi

IPC分类号： G01R31/28

CPC分类号： G01R31/318597 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/3202

摘要： A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. The test vector is input from the memory to the embedded core to mimic scan chain input to the embedded core. A test result is obtained from the embedded core responsive in part to the test vector input.

摘要翻译： 描述了集成电路（“IC”）的嵌入式核心的测试方法。 IC具有在IC中彼此耦合的硬连线的嵌入式核心和存储器。 该方法包括在嵌入式核心工作时将测试向量写入存储器。 测试向量从存储器输入到嵌入式核心，以模拟到嵌入式核心的扫描链输入。 测试结果从嵌入式核心获得部分响应于测试矢量输入。

公开(公告)号：US07219287B1

公开(公告)日：2007-05-15

申请号：US10955560

申请日：2004-09-29

申请人： Shahin Toutounchi ,  Andrew M. Taylor

发明人： Shahin Toutounchi ,  Andrew M. Taylor

IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F19/00 ,  G06F15/00

CPC分类号： G01R31/31835 ,  G01R31/318516 ,  Y10S707/99953

摘要： A method and apparatus are disclosed that simplify and reduce the time required for detecting faults in a programmable device such as a programmable logic device (PLD) by utilizing fault coverage information corresponding to a plurality of test patterns for the PLD to reduce the set of potential faults. For one embodiment, each test pattern is designated as either passing or failing, the faults that are detectable by at least two failing test patterns and the faults that are not detectable by any passing test patterns are eliminated, and the remaining faults are diagnosed. For another embodiment, the faults detectable by each failing test pattern are diagnosed to generate corresponding fault sets, and the faults not common to the fault sets and not detectable by one or more of the failing test patterns are eliminated.

摘要翻译： 公开了一种方法和装置，其通过利用与PLD的多个测试模式对应的故障覆盖信息来简化和减少检测诸如可编程逻辑器件（PLD）的可编程设备中的故障所需的时间，以减少潜在的电位 故障 对于一个实施例，将每个测试模式指定为通过或失败，可以消除由至少两个故障测试模式可检测的故障，并且消除由任何通过的测试模式无法检测到的故障，并且诊断剩余的故障。 对于另一个实施例，可以诊断每个故障测试模式可检测到的故障以产生相应的故障集，并且消除由一个或多个故障测试模式不能检测到的故障集合不常见的故障。

公开(公告)号：US06732309B1

公开(公告)日：2004-05-04

申请号：US09921115

申请日：2001-08-02

申请人： Shahin Toutounchi ,  Andrew W. Lai

发明人： Shahin Toutounchi ,  Andrew W. Lai

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： A new method to test short faults in a programmable logic device is described. The line segments under test are connected together to form a conducting chain. All the line segments neighboring to the conducting chain are tied to a known state. A test vector is applied to the programmable logic device. The state of the line under test is measured. If it is the same as the known state, the programmable logic device is likely to have faults.

摘要翻译： 描述了一种在可编程逻辑器件中测试短路故障的新方法。 被测线路连接在一起形成导电链。 与导向链相邻的所有线段被绑定到已知状态。 将测试矢量应用于可编程逻辑器件。 测量被测线路的状态。 如果与已知状态相同，则可编程逻辑器件可能存在故障。

公开(公告)号：US07544968B1

公开(公告)日：2009-06-09

申请号：US11210499

申请日：2005-08-24

申请人： Shahin Toutounchi ,  James Karp ,  Jongheon Jeong ,  Michael G. Ahrens ,  Michael J. Hart

发明人： Shahin Toutounchi ,  James Karp ,  Jongheon Jeong ,  Michael G. Ahrens ,  Michael J. Hart

IPC分类号： H01L29/04

CPC分类号： H01L29/42368 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11206

摘要： An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.

摘要翻译： MOS晶体管被编程在非易失性存储单元中。 非易失性存储单元中的存储电容器用于通过在栅极电介质击穿期间向MOS晶体管的编程端提供额外的电荷来提高编程效率，从而避免软编程故障。 在特定实施例中，存储电容器是具有比可编程MOS晶体管的介电层更厚的栅介质层的第二MOS晶体管。