公开(公告)号：US20170270496A1

公开(公告)日：2017-09-21

申请号：US15602058

申请日：2017-05-22

Applicant: Dyron Clower ,  John Templer ,  La Shonna Sharp ,  Aaron Calipari ,  Michael Ring ,  Michael Serrette ,  Nickolas Ledford ,  Lawrence Dugger ,  Rodney Drake ,  Diana Hayes

Inventor： Dyron Clower ,  John Templer ,  La Shonna Sharp ,  Aaron Calipari ,  Michael Ring ,  Michael Serrette ,  Nickolas Ledford ,  Lawrence Dugger ,  Rodney Drake ,  Diana Hayes

IPC: G06Q20/10

CPC classification number: G06Q20/1085 ,  G06Q20/042 ,  G06Q20/3223 ,  G06Q20/40145 ,  G06Q20/4016 ,  G06Q20/405 ,  G06Q40/02

Abstract: A real-time system and method for determining whether to invoke a fraud alert notification to a bank concerning an account holder or an item issuer following an interim determination that the account holder or item issuer has participated in a fraudulent transaction. An interim determination is updated based in part on bank transaction data received following the interim determination.

公开(公告)号：US06230275B1

公开(公告)日：2001-05-08

申请号：US09232053

申请日：1999-01-15

Applicant: Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

Inventor： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

IPC: G06F126

CPC classification number: G11C5/14 ,  G11C7/1045 ,  H03K19/0016

Abstract: A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

Abstract translation: 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。

公开(公告)号：US5469557A

公开(公告)日：1995-11-21

申请号：US26967

申请日：1993-03-05

Applicant: Tom Salt ,  Rodney Drake

Inventor： Tom Salt ,  Rodney Drake

IPC: G11C8/20 ,  G11C16/22 ,  G06F12/14 ,  H04L9/00

CPC classification number: G11C8/20 ,  G11C16/22

Abstract: A semiconductor microcontroller device is adapted to control the operation of an external system. The device includes a CPU, program memory for storing instructions to be executed by the CPU to perform its control functions, and data memory for storing data for selective retrieval by the CPU. The contents of either memory are code protected by an EEPROM fuse, and are automatically erased if the code protect state of the EEPROM fuse is sought to be reset, and the EEPROM fuse is reset only after the erasure of the memory contents.

Abstract translation: 半导体微控制器装置适于控制外部系统的操作。 该设备包括CPU，用于存储要由CPU执行以执行其控制功能的指令的程序存储器，以及用于存储用于CPU选择性检索的数据的数据存储器。 任何一个存储器的内容均由EEPROM保险丝进行代码保护，如果要求复位EEPROM保险丝的代码保护状态，并且只有擦除存储器内容之后EEPROM保险丝才会被复位。

公开(公告)号：US5874931A

公开(公告)日：1999-02-23

申请号：US671962

申请日：1996-06-28

Applicant: Rodney Drake ,  Ray Allen

Inventor： Rodney Drake ,  Ray Allen

IPC: G02F1/133 ,  G06F3/147 ,  G09G3/18 ,  G09G3/20 ,  G09G3/36

CPC classification number: G06F3/147 ,  G09G3/18 ,  G09G3/3696

Abstract: A single semiconductor chip device is utilized for controlling an external system which has a liquid crystal display (LCD) associated therewith. A dual port random access memory (RAM) stores data representative of information to be displayed on the LCD. The RAM includes a plurality of master data storage latches and a single slave data storage latch shared by all of the plurality of master storage latches. A microcontroller has a central processing unit (CPU) for communicating with the master storage latches via one of the RAM ports to periodically change the data stored therein. An LCD control module successively updates the data in the single slave storage latch with data from each of the master storage latches and downloads the updated data from the single slave storage latch to a temporary store associated with the LCD after each update from a master storage latch and before the update of data from the next master storage latch. Consequently, data in each master storage latch may be changed periodically by the CPU without interference with downloading of updated data from the single slave storage unit.

Abstract translation: 单个半导体芯片装置用于控制具有与其相关联的液晶显示器（LCD）的外部系统。 双端口随机存取存储器（RAM）存储表示要显示在LCD上的信息的数据。 RAM包括多个主数据存储锁存器和由所有多个主存储锁存器共享的单个从属数据存储锁存器。 微控制器具有中央处理单元（CPU），用于经由一个RAM端口与主存储锁存器进行通信，以周期性地改变存储在其中的数据。 LCD控制模块使用来自每个主存储锁存器的数据连续地更新单个从存储锁存器中的数据，并且在从主存储器锁存器每次更新之后将更新的数据从单个从存储锁存器下载到与LCD相关联的临时存储器 并在更新下一个主存储锁存器的数据之前。 因此，每个主存储锁存器中的数据可以由CPU周期性地改变，而不会干扰来自单个从存储单元的更新数据的下载。

公开(公告)号：US5870409A

公开(公告)日：1999-02-09

申请号：US671011

申请日：1996-06-28

Applicant: Randy Yach ,  Rodney Drake

Inventor： Randy Yach ,  Rodney Drake

IPC: G01R31/00 ,  G02F1/13 ,  G02F1/133 ,  G06F11/267 ,  G09G3/00 ,  G09G3/36 ,  H04N5/66 ,  G01R31/28

CPC classification number: G09G3/006 ,  G06F11/2221

Abstract: A method is disclosed for testing a high speed microcontroller fabricated on a semiconductor chip, and for testing relatively low speed functions of a liquid crystal display (LCD) module on the chip that drives an off-chip LCD for an external system to be controlled by the microcontroller with a plurality of discrete analog voltage levels for performing the LCD functions. Digital values are multiplexed in time slots of a test waveform to simulate in high speed digital format of a test mode the low speed timing, relative magnitude and functionality of analog voltage levels used to drive the LCD; A high speed driver is selectively coupled to a pin of the chip, to which the discrete analog voltage levels are normally applied at low speed to drive the LCD, and the test waveform is applied to the high speed driver. The digital values and timing that appear on the pin are then monitored as an indication of proper functionality of the LCD module. The high speed driver is switched out and the normal low speed LCD driver is switched back for return to an LCD user mode when the test mode is completed. Monitoring the pin with a digital tester allows verification that pin pulses in predetermined time slots indicate the corresponding analog voltage level is being applied at the proper time during normal operation of the LCD module, and digitally testing of continuity in an analog channel. A transistor normally employed on the chip for electrostatic discharge protection is activated to selectively couple the high speed driver to the pin for the high speed testing mode.

Abstract translation: 公开了一种用于测试在半导体芯片上制造的高速微控制器的方法，并且用于测试芯片上的液晶显示器（LCD）模块的相对低速功能，该芯片驱动用于外部系统的片外LCD以由 具有用于执行LCD功能的多个离散模拟电压电平的微控制器。 数字值在测试波形的时隙中进行多路复用，以模拟用于驱动LCD的模拟电压电平的低速定时，相对幅度和功能的测试模式的高速数字格式; 选择性地将高速驱动器耦合到芯片的引脚，通过低速驱动分立的模拟电压电平来驱动LCD，测试波形被施加到高速驱动器。 然后监视引脚上出现的数字值和时序作为LCD模块正常功能的指示。 当测试模式完成时，高速驱动器被切换并且正常的低速LCD驱动器被切回以返回到LCD用户模式。 使用数字测试仪监控引脚，可以验证在预定时隙内的引脚脉冲表示在LCD模块正常工作期间的适当时间正在施加相应的模拟电压电平，并对模拟通道的连续性进行数字测试。 通常在芯片上用于静电放电保护的晶体管被​​激活以选择性地将高速驱动器耦合到用于高速测试模式的引脚。

公开(公告)号：US5473758A

公开(公告)日：1995-12-05

申请号：US938911

申请日：1992-08-31

Applicant: Ray Allen ,  Sumit Mitra ,  Rodney Drake

Inventor： Ray Allen ,  Sumit Mitra ,  Rodney Drake

IPC: G11C16/10 ,  G06F15/02

CPC classification number: G11C16/102

Abstract: A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.

Abstract translation: 在单个半导体芯片中制造微控制器和相关联的EPROM程序存储器。 微控制器设备适于在使用要由设备控制的系统安装设备的电路中的数字命令字或其他位模式中使用数字命令字或其他位模式进行编程，并将其编程引脚与系统隔离以避免对 系统运行时正在进行编程。 在线编程使用量远低于设备的输入/输出（I / O）引脚总数，总共少于命令字中的位数。 这是通过引脚和程序存储器之间的串行/并行编程接口实现的，并且通过将数据以串行方式应用于其被锁存并且并行加载到存储器中的接口来实现。 输入到设备的数据可以替代地以与字节相同的字节并行输入，该字节的宽度小于设备的I / O引脚的总数。

公开(公告)号：US5351216A

公开(公告)日：1994-09-27

申请号：US26908

申请日：1993-03-05

Applicant: Tom Salt ,  Rodney Drake ,  Ray Allen

Inventor： Tom Salt ,  Rodney Drake ,  Ray Allen

IPC: G05B19/042 ,  G06F11/14 ,  G11C16/22 ,  G06K5/00

CPC classification number: G05B19/0428 ,  G06F11/1402 ,  G11C16/22 ,  G05B2219/23215 ,  G05B2219/23345 ,  G05B2219/25301

Abstract: A single chip, semiconductor microcontroller device is adapted to control an aspect of the operation of an external system. The device includes a CPU, program memory for storing instructions to be selectively executed by the CPU to perform the control functions, and peripheral EEPROM data memory adapted to be written to for storing selected data in selected ones of a multiplicity of addresses of the data memory and for selective retrieval of the stored dam by the CPU within its control function. Internal logic in the device is implemented to abort a write operation in progress on the EEPROM data memory upon occurrence of an asynchronous reset of the device. An error flag is set by the logic to indicate that the write operation is being aborted, and the data that was partially written to the EEPROM memory at the time the write operation was aborted is held intact.

Abstract translation: 单芯片半导体微控制器装置适于控制外部系统的操作的一个方面。 该装置包括CPU，用于存储由CPU选择性地执行以执行控制功能的指令的程序存储器，以及适于被写入以便将选择的数据存储在数据存储器的多个地址中的选定数据中的外围EEPROM数据存储器 并且用于在其控制功能内由CPU选择性地检索存储的水坝。 器件的内部逻辑被实现为在器件的异步复位发生时中止EEPROM数据存储器上正在进行的写入操作。 由逻辑设置错误标志以指示写入操作正在中止，并且在写入操作中止时部分写入EEPROM存储器的数据保持不变。