公开(公告)号：US08232162B2

公开(公告)日：2012-07-31

申请号：US12880419

申请日：2010-09-13

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang ,  Yanli Zhang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L21/8242

CPC分类号： H01L29/66181 ,  H01L27/1087

摘要： A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.

摘要翻译： 形成半导体器件的深沟槽结构的方法包括在半导体衬底上形成掩模层。 通过对掩模层进行构图来形成掩模层中的开口，并且使用掩模层中的图案化开口在半导体衬底中形成深沟槽。 牺牲填充材料形成在掩模层上并进入深沟槽中。 牺牲填充材料的第一部分从深沟槽凹陷，并且第一掺杂剂注入在半导体衬底中形成第一掺杂区域。 牺牲填充材料的第二部分从深沟槽凹陷，并且第二掺杂剂注入在半导体衬底中形成第二掺杂区，其中第二掺杂区形成在第一掺杂区的下方，使得第二掺杂区和第一掺杂区 掺杂区域彼此邻接。

公开(公告)号：US20120068237A1

公开(公告)日：2012-03-22

申请号：US12886224

申请日：2010-09-20

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.

摘要翻译： 在替代栅极集成方案中形成平坦化介电层之后，去除一次性栅极结构，并且在凹入的栅极区内形成栅极电介质层和栅极电极层的堆叠。 然后，每个栅极电极结构凹陷在栅极电介质层的最上表面之下。 通过平面化形成在每个栅电极上方的介电金属氧化物部分。 电介质金属氧化物部分和栅极间隔物用作自对准蚀刻掩模与图案化的光致抗蚀剂组合以在每个嵌入的存储器单元结构中暴露和金属化源极区域和内部电极的半导体表面。 金属化半导体部分形成金属半导体合金带，其在电容器的内部电极和存取晶体管的源之间提供导电路径。

公开(公告)号：US20110272762A1

公开(公告)日：2011-11-10

申请号：US12776829

申请日：2010-05-10

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66742 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.

摘要翻译： 填充深沟槽的节点电介质和导电沟槽填充区域凹陷到与绝缘体上半导体（SOI）层的顶表面基本上共面的深度。 浅沟槽隔离部分形成在深沟槽的上部的一侧上，而深沟槽的上部的另一侧提供导电填充区域的半导体材料的暴露表面。 执行选择性外延工艺以沉积升高的源极区域和升高的带状区域。 升高的源极区域直接形成在SOI层内的平坦的源极区域上，并且凸起的带区域直接形成在导电填充区域上。 升高的带区域接触升高的源极区域，以在平面源极区域和导电填充区域之间提供导电路径。

公开(公告)号：US08846470B2

公开(公告)日：2014-09-30

申请号：US13153538

申请日：2011-06-06

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/8242 ,  H01L49/02 ,  H01L21/762 ,  H01L29/66 ,  H01L21/74 ,  H01L27/06

CPC分类号： H01L27/10829 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/92 ,  H01L29/0649 ,  H01L29/66181

摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

摘要翻译： 提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。 该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。 该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。 该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。 该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。 该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

公开(公告)号：US08829585B2

公开(公告)日：2014-09-09

申请号：US13118881

申请日：2011-05-31

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Y. Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Y. Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L29/92 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1203

摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

摘要翻译： 在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料 的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。 可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

公开(公告)号：US08647945B2

公开(公告)日：2014-02-11

申请号：US12959824

申请日：2010-12-03

申请人： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

发明人： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC分类号： H01L21/70

CPC分类号： H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

摘要： A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

摘要翻译： 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。

公开(公告)号：US20120139080A1

公开(公告)日：2012-06-07

申请号：US12959824

申请日：2010-12-03

申请人： Geng Wang ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

发明人： Geng Wang ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC分类号： H01L21/70 ,  H01L21/20

CPC分类号： H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

摘要： A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

摘要翻译： 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。

公开(公告)号：US20120122315A1

公开(公告)日：2012-05-17

申请号：US12943956

申请日：2010-11-11

申请人： ROGER A. BOOTH, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： ROGER A. BOOTH, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/302 ,  G06F17/50 ,  H01L21/3205

CPC分类号： H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.

摘要翻译： 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和另一图案化线的图案转移到衬底。

公开(公告)号：US08575670B2

公开(公告)日：2013-11-05

申请号：US13316056

申请日：2011-12-09

申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L27/10861 ,  H01L28/91 ,  H01L29/945

摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.

摘要翻译： 一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。 电容器存在于沟槽的下部。 电介质垫片存在于沟槽上部的侧壁上。 介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。 导电材料填充物存在于沟槽的上部。 半导体器件存在于与沟槽相邻的SOI层上。 半导体器件通过导电材料填充与电容器电连通。

公开(公告)号：US09059248B2

公开(公告)日：2015-06-16

申请号：US13369382

申请日：2012-02-09

申请人： Joseph Ervin ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

发明人： Joseph Ervin ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A method of forming a semiconductor device including forming well trenches on opposing sides of a gate structure by removing portions of a semiconductor on insulator (SOI) layer of an semiconductor on insulator (SOI) substrate, wherein the base of the well trenches is provided by a surface of a buried dielectric layer of the SOI substrate and sidewalls of the well trenches are provided by a remaining portion of the SOI layer. Forming a dielectric fill material at the base of the well trenches, wherein the dielectric fill material is in contact with the sidewalls of the well trenches and at least a portion of the surface of the buried dielectric layer that provides the base of the well trenches. Forming a source region and a drain region in the well trenches with an in-situ doped epitaxial semiconductor material.

摘要翻译： 一种形成半导体器件的方法，包括通过去除绝缘体上半导体（SOI）衬底上的半导体绝缘体（SOI）层的部分，在栅极结构的相对侧上形成阱沟，其中阱沟的基极由 SOI衬底的掩埋介电层的表面和阱沟的侧壁由SOI层的剩余部分提供。 在阱沟的底部形成介电填充材料，其中介质填充材料与阱沟槽的侧壁和提供阱沟的基底的掩埋介电层的表面的至少一部分接触。 在原位掺杂的外延半导体材料的阱沟中形成源极区和漏极区。