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11.发明授权Method and system for improving data coherency in a parallel rendering system 有权用于提高并行渲染系统中数据一致性的方法和系统公开(公告)号：US08139069B1
公开(公告)日：2012-03-20
申请号：US11556660
申请日：2006-11-03
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳 的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。
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公开(公告)号：US07663621B1
公开(公告)日：2010-02-16
申请号：US11556515
申请日：2006-11-03
CPC分类号： G06T15/04
摘要： Circuits, methods, and apparatus that perform cylindrical wrapping in software without the need for a dedicated hardware circuit. One example performs cylindrical wrapping in software running on shader hardware. In one specific example, the shader hardware is a unified shader that alternately processes geometry, vertex, and fragment information. This unified shader is formed using a number of single-instruction, multiple-data units. Another example provides a method of performing a cylindrical wrap that ensures that a correct texture portion is used for a triangle that is divided by a “seam” of the wrap. To achieve this, primitive vertices are sorted such that results are vertex order invariant. One vertex is selected as a reference. For the other vertices, a difference is found for each coordinate and a corresponding coordinate of the reference vertex. If the coordinates are near, no change is made. If the coordinates are distant, the coordinate is adjusted.
摘要翻译： 在软件中执行圆柱形包装而不需要专用硬件电路的电路，方法和装置。 一个例子是在着色器硬件上运行的软件中执行圆柱包装。 在一个具体的例子中，着色器硬件是一个统一的着色器，交替地处理几何，顶点和片段信息。 这个统一着色器是使用多个单指令多数据单元形成的。 另一个例子提供了一种执行圆柱形包装的方法，该方法确保将正确的纹理部分用于由包裹的“接缝”划分的三角形。 为了实现这一点，原始顶点被排序，使得结果是顶点顺序不变的。 选择一个顶点作为参考。 对于其他顶点，对于每个坐标和参考顶点的相应坐标找到一个差异。 如果坐标靠近，则不进行任何更改。 如果坐标较远，则调整坐标。
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13.发明授权公开(公告)号：US08134570B1
公开(公告)日：2012-03-13
申请号：US11532779
申请日：2006-09-18
申请人： Jerome F. Duluk, Jr. , Andrew J. Tao , Roger L. Allen , Svetoslav D. Tzvetkov , Yan Yan Tang , Elena M. Ing
发明人： Jerome F. Duluk, Jr. , Andrew J. Tao , Roger L. Allen , Svetoslav D. Tzvetkov , Yan Yan Tang , Elena M. Ing
IPC分类号： G09G5/00
CPC分类号： G06T15/005
摘要： A system, method and computer program product are provided for packing graphics attributes. In use, a plurality of graphics attributes is identified. Such graphics attributes are packed, such that the packed graphics attributes are capable of being processed utilizing a pixel shader.
摘要翻译： 提供了用于打包图形属性的系统，方法和计算机程序产品。 在使用中，识别出多个图形属性。 打包这样的图形属性，使得打包的图形属性能够利用像素着色器进行处理。
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公开(公告)号：US07877565B1
公开(公告)日：2011-01-25
申请号：US11344445
申请日：2006-01-31
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/383
摘要： Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.
摘要翻译： 在多线程处理器中使用多个版本的可编程常数的系统和方法允许在使用常数的程序完成执行之前更改可编程常数。 可以提高处理性能，因为对可编程常数使用不同值的程序可以同时执行。 可编程常数存储在常量缓冲区中，常数缓冲表的条目被绑定到常量缓冲区。 当可编程常数被更改时，它被复制到页面池中的条目，并且页面池的地址转换被更新为对应于可编程常数的旧版本（复制）。 一个优点是常量缓冲存储最新版本的可编程常数。
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15.发明授权公开(公告)号：US07600155B1
公开(公告)日：2009-10-06
申请号：US11302950
申请日：2005-12-13
IPC分类号： G06F11/00
CPC分类号： G06F11/36
摘要： A system has a graphics processing unit with a processor to monitor selected criteria and circuitry to initiate the storage of execution state information when the selected criteria reaches a specified state. A memory stores execution state information. A central processing unit executes a debugging program to analyze the execution state information.
摘要翻译： 系统具有图形处理单元，其具有处理器以监视所选标准和电路，以在所选标准达到指定状态时启动执行状态信息的存储。 内存存储执行状态信息。 中央处理单元执行调试程序以分析执行状态信息。
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公开(公告)号：US07542042B1
公开(公告)日：2009-06-02
申请号：US10985575
申请日：2004-11-10
CPC分类号： G06T1/20 , G06F9/5044 , G06T15/005 , G09G5/14 , G09G2360/121 , G09G2360/18
摘要： A new method of operating a fragment shader to produce complex video content comprised of a video image or images, such as from a DVD player, that overlays a fragment shader-processed background. Pixels are fragment shader-processed during one loop or set of loops through a texture processing stations to produce a fragment shader-processed background. Then, at least some of those pixels are merged with the video or images to produce complex video content. The resulting complex image is then made available for further processing.
摘要翻译： 操作片段着色器以产生由视频图像或诸如DVD播放器的图像组成的复杂视频内容的新方法，其叠加片段着色器处理的背景。 像素是通过纹理处理站的一个循环或一组循环中的片段着色器处理，以产生片段着色器处理的背景。 然后，这些像素中的至少一些与视频或图像合并以产生复杂的视频内容。 然后使得到的复杂图像可用于进一步处理。
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17.发明申请METHOD AND SYSTEM FOR IMPROVING DATA COHERENCY IN A PARALLEL RENDERING SYSTEM 有权用于提高并行渲染系统中的数据相关性的方法和系统公开(公告)号：US20120147027A1
公开(公告)日：2012-06-14
申请号：US13399458
申请日：2012-02-17
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳 的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。
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公开(公告)号：US08094158B1
公开(公告)日：2012-01-10
申请号：US11344306
申请日：2006-01-31
IPC分类号： G06F13/00
CPC分类号： G06F9/3832 , G06F9/3851 , G06F12/0292 , G06T1/20
摘要： Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.
摘要翻译： 在多线程处理器中使用多个版本的可编程常数的系统和方法允许在使用常数的程序完成执行之前更改可编程常数。 可以提高处理性能，因为对可编程常数使用不同值的程序可以同时执行。 可编程常数存储在常量缓冲区中，常数缓冲表的条目被绑定到常量缓冲区。 当可编程常数被更改时，它被复制到页面池中的条目，并且页面池的地址转换被更新为对应于可编程常数的旧版本（复制）。 一个优点是常量缓冲存储最新版本的可编程常数。
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19.发明授权Method and system for improving data coherency in a parallel rendering system 有权用于提高并行渲染系统中数据一致性的方法和系统公开(公告)号：US08085272B1
公开(公告)日：2011-12-27
申请号：US11556657
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.
摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记 基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性 公共输入流。 每个片段流被独立地处理并对应于其中一个ROP请求流。
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公开(公告)号：US07852340B2
公开(公告)日：2010-12-14
申请号：US11957358
申请日：2007-12-14
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译： 公开了可扩展着色器架构。 根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。 着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。 着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。 着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。 着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。 每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。
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