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    OUTPUT FEEDBACK CONTROL CIRCUIT
    13.
    发明申请
    OUTPUT FEEDBACK CONTROL CIRCUIT 有权

    公开(公告)号：US20220393596A1

    公开(公告)日：2022-12-08

    申请号：US17777137

    申请日：2020-12-03

    Applicant: Rohm Co., Ltd.

    Inventor： Isao Takobe ,  Masashi Nagasato

    IPC: H02M3/158 ,  H02M1/00 ,  H02M1/08

    Abstract: An output feedback control circuit includes, as a means for generating an error signal ERR between a feedback voltage FB commensurate with an output voltage and a reference voltage REF (means for substituting for a single error amplifier 140), a first signal processor (for example, an amplifier 140a) that forms a first path, and a second signal processor (for example, an amplifier 140b) that forms a second path. The amplifier 140a is more accurate than the amplifier 140b, and the amplifier 140b is faster than the amplifier 140a. To the output terminal of the amplifier 140a, preferably, a capacitor Cc other than a parasitic element is connected. To the output terminal of the amplifier 140b, preferably, no capacitor other than a parasitic element is connected, and a resistor Rc is connected. Preferably, the amplifier 140a has a transconductance gm1, and the amplifier 140b has a transconductance gm2 (≠gm1).

    SWITCHING POWER SUPPLY, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND DIFFERENTIAL INPUT CIRCUIT
    14.
    发明申请
    SWITCHING POWER SUPPLY, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND DIFFERENTIAL INPUT CIRCUIT 有权

    公开(公告)号：US20210257978A1

    公开(公告)日：2021-08-19

    申请号：US17056314

    申请日：2018-12-18

    Applicant: Rohm Co., Ltd.

    Inventor： Masashi Nagasato ,  Seiji Takenaka ,  Tetsuo Tateishi

    IPC: H03F3/45 ,  H02M3/158 ,  H03F1/52 ,  H03F3/217

    Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

    Printed wiring board
    15.
    发明授权
    Printed wiring board 有权

    公开(公告)号：US10856406B2

    公开(公告)日：2020-12-01

    申请号：US15099905

    申请日：2016-04-15

    Applicant: Rohm Co., Ltd.

    Inventor： Masashi Nagasato

    IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46

    Abstract: A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.

    SEMICONDUCTOR DEVICE
    16.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180183374A1

    公开(公告)日：2018-06-28

    申请号：US15905345

    申请日：2018-02-26

    Applicant: Rohm Co., Ltd.

    Inventor： Masashi Nagasato

    IPC: H02P27/04 ,  H03K17/687 ,  H01L23/64

    Abstract: A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.

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