公开(公告)号：US08187962B2

公开(公告)日：2012-05-29

申请号：US12754294

申请日：2010-04-05

Applicant: Roland Hampp

Inventor： Roland Hampp

IPC: H01L21/3205

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

公开(公告)号：US07795107B2

公开(公告)日：2010-09-14

申请号：US12552352

申请日：2009-09-02

Applicant: Roland Hampp ,  Alois Gutmann ,  Jin-Ping Han ,  O Sung Kwon

Inventor： Roland Hampp ,  Alois Gutmann ,  Jin-Ping Han ,  O Sung Kwon

IPC: H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

Abstract: A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.

Abstract translation: 在所提供的半导体本体的表面中形成沟槽。 在沟槽中沉积氧化物，并且在氧化物上沉积帽，其中帽和氧化物的组合在半导体本体上赋予机械应力。

公开(公告)号：US20090317957A1

公开(公告)日：2009-12-24

申请号：US12552352

申请日：2009-09-02

Applicant: Roland Hampp ,  Alois Gutmann ,  Jin-Ping Han ,  O Sung Kwon

Inventor： Roland Hampp ,  Alois Gutmann ,  Jin-Ping Han ,  O Sung Kwon

IPC: H01L21/762 ,  H01L21/336

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

Abstract: A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.

Abstract translation: 在所提供的半导体本体的表面中形成沟槽。 在沟槽中沉积氧化物，并且在氧化物上沉积帽，其中帽和氧化物的组合在半导体本体上赋予机械应力。

公开(公告)号：US20080315267A1

公开(公告)日：2008-12-25

申请号：US11766234

申请日：2007-06-21

Applicant: Roland Hampp ,  Alois Gutmann ,  Jin-Ping Han ,  O Sung Kwon

Inventor： Roland Hampp ,  Alois Gutmann ,  Jin-Ping Han ,  O Sung Kwon

IPC: H01L29/94 ,  H01L21/76 ,  H01L29/06

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

Abstract: A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.

Abstract translation: 在所提供的半导体本体的表面中形成沟槽。 在沟槽中沉积氧化物，并且在氧化物上沉积帽，其中帽和氧化物的组合在半导体本体上赋予机械应力。

公开(公告)号：US20080311711A1

公开(公告)日：2008-12-18

申请号：US11818197

申请日：2007-06-13

Applicant: Roland Hampp ,  Jun-Keun Kwak ,  Keith Kwong Hon Wong

Inventor： Roland Hampp ,  Jun-Keun Kwak ,  Keith Kwong Hon Wong

IPC: H01L21/4763 ,  H01L21/336

CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/76814 ,  H01L21/76865 ,  H01L23/485 ,  H01L29/665 ,  H01L29/7833

Abstract: A method of making a semiconductor interconnect is disclosed. A semiconductor body on which a transistor comprising a doped region is formed is provided. A dielectric region is formed over the doped region, and a contact hole is formed in the dielectric to expose the doped region. The contact hole is cleaned and a first layer of metal is formed over a bottom and sidewalls of the contact hole. The first layer of metal is thinned so that the thickness of the first layer of metal on the sidewalls is made more uniform. A barrier is formed over the first layer of metal and the contact hole is filled with conductive material.

Abstract translation: 公开了制造半导体互连的方法。 提供了形成有包括掺杂区域的晶体管的半导体主体。 在掺杂区域上形成电介质区域，并且在电介质中形成接触孔以暴露掺杂区域。 接触孔被清洁，第一层金属形成在接触孔的底部和侧壁上。 使第一金属层变薄，使得侧壁上的第一金属层的厚度更均匀。 在第一金属层上形成屏障，并且接触孔填充有导电材料。

公开(公告)号：US20070087560A1

公开(公告)日：2007-04-19

申请号：US11251180

申请日：2005-10-14

Applicant: Jun-keun Kwak ,  Roland Hampp

Inventor： Jun-keun Kwak ,  Roland Hampp

IPC: H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76895

Abstract: Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate support in a process chamber, pre-heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 60 seconds or more, forming a silicon protective layer on the substrate by supplying a silicon source gas into the process chamber and heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 10 seconds or more, and forming a tungsten layer on the silicon protective layer.

Abstract translation: 提供一种制造具有增强的电气特性的半导体器件的方法。 该方法包括将衬底设置在处理室中的衬底支撑件上，预热衬底上的衬底，调节到300-400℃的温度达60秒以上，在衬底上形成硅保护层，通过 将硅源气体供应到处理室中，并加热调节至300-400℃温度的衬底支撑体上的衬底10秒以上，并在硅保护层上形成钨层。

公开(公告)号：US20120126343A1

公开(公告)日：2012-05-24

申请号：US13365418

申请日：2012-02-03

Applicant: Roland Hampp

Inventor： Roland Hampp

IPC: H01L29/78 ,  H01L29/41 ,  H01L29/45

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

Abstract translation: 公开了形成自对准硅化物触点的结构和方法。 该结构包括设置在有源区上的栅电极，设置在栅极上的衬垫和有源区的至少一部分，设置在衬垫上的绝缘层。 第一接触插塞设置在绝缘层和衬垫中，第一接触插头设置在有源区域的一部分上方并与其接触，第一接触插塞包括第一导电材料。 第二接触插塞设置在绝缘层和衬垫中，第二接触插塞设置在栅电极的一部分上方并与其接触，第二接触插塞包括第一导电材料。 接触材料层设置在有源区域中，接触材料层设置在第一接触插塞下方并且包括第一导电材料。

公开(公告)号：US20110175148A1

公开(公告)日：2011-07-21

申请号：US13074888

申请日：2011-03-29

Applicant: Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

Inventor： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

IPC: H01L29/772

CPC classification number: H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

Abstract translation: 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。

公开(公告)号：US20090227086A1

公开(公告)日：2009-09-10

申请号：US12043384

申请日：2008-03-06

Applicant: Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

Inventor： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

IPC: H01L21/76

CPC classification number: H01L21/76262 ,  H01L21/76278

Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

Abstract translation: 公开了STI模型中的有源面积损耗的防止，这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽，半导体材料被进一步处理以产生多个有源器件。 因此，有源器件是在图案化电介质中产生的，而不是在有源器件的半导体衬底中产生的STI。

公开(公告)号：US20090218640A1

公开(公告)日：2009-09-03

申请号：US12040409

申请日：2008-02-29

Applicant: Roland Hampp

Inventor： Roland Hampp

IPC: H01L29/78 ,  H01L23/48 ,  H01L21/3205

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

Abstract translation: 公开了形成自对准硅化物触点的结构和方法。 该结构包括设置在有源区上的栅电极，设置在栅极上的衬垫和有源区的至少一部分，设置在衬垫上的绝缘层。 第一接触插塞设置在绝缘层和衬垫中，第一接触插头设置在有源区域的一部分上方并与其接触，第一接触插塞包括第一导电材料。 第二接触插塞设置在绝缘层和衬垫中，第二接触插塞设置在栅电极的一部分上方并与其接触，第二接触插塞包括第一导电材料。 接触材料层设置在有源区域中，接触材料层设置在第一接触插塞下方并且包括第一导电材料。