公开(公告)号：US07831808B2

公开(公告)日：2010-11-09

申请号：US11961914

申请日：2007-12-20

Applicant: Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  David Shippy

Inventor： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  David Shippy

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3885 ,  G06F9/3887

Abstract: A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.

Abstract translation: 处理器包括适于接收和配置为执行GP指令的通用（GP）单元; 并且包括适于接收和配置为执行SIMD指令的单指令多数据（SIMD）单元。 指令单元包括耦合到GP单元的第一逻辑单元和耦合到SIMD单元的第二逻辑单元，其中在GP指令之后处理SIMD指令。 在第一个逻辑单元中，具有未解决的依赖关系的GP指令无条件地导致后续的SIMD指令停止，并且具有未解决依赖性的SIMD指令不会导致后续的GP指令停止。 第一个逻辑单元解决GP指令中的依赖关系，向GP单元提供无依赖指令，并向第二个逻辑单元提供SIMD指令。 第二个逻辑单元解决SIMD指令中的依赖关系，并向SIMD单元提供无依赖指令。

公开(公告)号：US07490224B2

公开(公告)日：2009-02-10

申请号：US11246587

申请日：2005-10-07

Applicant: Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

Inventor： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

Abstract: Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.

Abstract translation: 介绍使用计数器跟踪发出的指令的顺序。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

公开(公告)号：US20080065873A1

公开(公告)日：2008-03-13

申请号：US11530612

申请日：2006-09-11

Applicant: Ronald Hall ,  Michael L. Karm ,  Alvan W. Ng ,  Todd A. Venton

Inventor： Ronald Hall ,  Michael L. Karm ,  Alvan W. Ng ,  Todd A. Venton

IPC: G06F9/44

CPC classification number: G06F9/3842 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3867 ,  G06F12/0891

Abstract: A method for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of the delay stage(s) in order to alter the “harmonic” fixed-cycle loop behavior. The livelock detection logic (LDL) counts the number of flushes a particular instruction takes or the number of times an instruction re-issues without completing. The LDL then compares that number to a preset threshold number. Based on the result of the comparison, the LDL triggers the implementation of one of two different livelock resolution processes. These processes include dynamically configuring the delay queue within the processor into one of two different configurations and changing the sequence and timing of handling memory access instructions, based on the specific configuration of the delay queue.

Abstract translation: 一种用于解决处理器核心和存储器子系统控制器之间的接口处的活动锁定的发生的方法。 通过在处理器内引入动态锁定检测机制（包括活动锁定检测实用程序或逻辑）来解决活锁，以检测活动锁定状态并动态地改变延迟阶段的持续时间，以便改变“谐波”固定循环回路 行为。 活动锁定检测逻辑（LDL）计算特定指令的刷新次数或指令重新发出而不完成的次数。 然后，LDL将该数字与预设的阈值数进行比较。 基于比较的结果，LDL触发了两种不同的动态锁定解析过程之一的实现。 这些过程包括基于延迟队列的具体配置，将处理器内的延迟队列动态地配置为两种不同配置之一并且改变处理存储器访问指令的顺序和定时。

公开(公告)号：US20070245350A1

公开(公告)日：2007-10-18

申请号：US11279775

申请日：2006-04-14

Applicant: Christopher Abernathy ,  Kurt Feiste ,  Ronald Hall ,  Albert Van Norstrand

Inventor： Christopher Abernathy ,  Kurt Feiste ,  Ronald Hall ,  Albert Van Norstrand

IPC: G06F9/46

CPC classification number: G06F9/524

Abstract: A system and method for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.

Abstract translation: 提供了一种用于将处理器置于逐渐减速操作模式的系统和方法。 逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。 处理器逐渐减速使处理器能够突破活动锁定状态。 此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。 说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

公开(公告)号：US20070245129A1

公开(公告)日：2007-10-18

申请号：US11279777

申请日：2006-04-14

Applicant: Christopher Abernathy ,  Kurt Feiste ,  Ronald Hall ,  Albert Van Norstrand

Inventor： Christopher Abernathy ,  Kurt Feiste ,  Ronald Hall ,  Albert Van Norstrand

IPC: G06F15/00

CPC classification number: G06F9/3867 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861

Abstract: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.

Abstract translation: 提供了一种用于将处理器置于逐渐减速操作模式的问题单元。 逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。 处理器逐渐减速使处理器能够突破活动锁定状态。 此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。 说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

公开(公告)号：US09772851B2

公开(公告)日：2017-09-26

申请号：US11923709

申请日：2007-10-25

Applicant: Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

Inventor： Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

IPC: G06F9/40 ,  G06F1/32 ,  G06F9/38 ,  G06F9/32 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3802 ,  G06F1/3234 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method, system, and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycles of the single branch, backwards short loop, rather than from the instruction cache.

公开(公告)号：US09395995B2

公开(公告)日：2016-07-19

申请号：US13408739

申请日：2012-02-29

Applicant: Ronald Hall ,  Michael L Karm ,  Brian R Mestan ,  David Mui

Inventor： Ronald Hall ,  Michael L Karm ,  Brian R Mestan ,  David Mui

IPC: G06F9/40 ,  G06F1/32 ,  G06F9/38 ,  G06F9/32

CPC classification number: G06F9/3802 ,  G06F1/3234 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method, system, and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycles of the single branch, backwards short loop, rather than from the instruction cache.

Abstract translation: 一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。 修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 处理器的指令单元中的指令取出在单个分支，向后的短循环的循环周期内，而不是从指令高速缓存中，从修改的缓冲器中检索短循环的指令。

公开(公告)号：US09052910B2

公开(公告)日：2015-06-09

申请号：US12132517

申请日：2008-06-03

Applicant: Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

Inventor： Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

IPC: G06F9/38

CPC classification number: G06F9/381 ,  G06F9/3814 ,  G06F9/3851

Abstract: A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.

Abstract translation: 设计结构提供了处理器指令单元内的指令获取，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。 修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 指令在循环周期长度存储在修改后的指令缓冲区中。 处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

公开(公告)号：US20150090466A1

公开(公告)日：2015-04-02

申请号：US14566275

申请日：2014-12-10

Applicant: Ronald Hall

Inventor： Ronald Hall

IPC: E02F5/32 ,  A01B13/08

CPC classification number: E02F5/326 ,  A01B13/08

Abstract: In an aspect of the invention a ripping mechanism for a vehicle is provided which includes a support frame, a ripping member, a vibrator mechanism, a pressure sensor, and a control system. The control system is configured to determine when the ripping member is engaged with hard material using the pressure sensor. When the ripping member is engaged with hard material, the control system is configured to permit operation of the vibrator mechanism. In some embodiments, the control system may further be configured to automatically start the vibrator mechanism when it detects that the ripping member is engaged with hard material. When the ripping member is not engaged with hard material, the control system is configured to deactivate the vibrator mechanism. In some embodiments, deactivation of the vibrator mechanism means that the control system turns off the vibrator mechanism. In some other embodiments, deactivation of the vibrator mechanism means that the control system prevents operation of the vibrator mechanism. In yet other embodiments deactivation of the vibrator mechanism may entail both turning off the vibrator mechanism and preventing operation of the vibrator mechanism. In yet other embodiments, the control system may include a switch that permits a vehicle operator to select which of these aforementioned actions the control system takes when determining that the ripping member is not engaged with hard material.

Abstract translation: 在本发明的一个方面，提供了一种用于车辆的翻录机构，其包括支撑框架，撕开构件，振动器机构，压力传感器和控制系统。 控制系统被配置为使用压力传感器来确定撕裂构件何时与硬质材料接合。 当撕裂构件与硬质材料接合时，控制系统构造成允许振动器机构的操作。 在一些实施例中，控制系统还可以被配置为当其检测到撕裂构件与硬质材料接合时，自动启动振动器机构。 当撕裂构件不与硬质材料接合时，控制系统被配置为停用振动器机构。 在一些实施例中，振动器机构的去激活意味着控制系统关闭振动器机构。 在一些其它实施例中，振动器机构的去激活意味着控制系统防止振动器机构的操作。 在另外的实施例中，振动器机构的停用可能需要关闭振动器机构并防止振动器机构的操作。 在其他实施例中，控制系统可以包括开关，其允许车辆操作者在确定撕开构件未与硬质材料接合时选择控制系统采取哪些上述动作。

公开(公告)号：US08131980B2

公开(公告)日：2012-03-06

申请号：US12132494

申请日：2008-06-03

Applicant: Ronald Hall ,  Michael L. Karm ,  Alvan W. Ng ,  Todd A. Venton

Inventor： Ronald Hall ,  Michael L. Karm ,  Alvan W. Ng ,  Todd A. Venton

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC classification number: G06F9/3861 ,  G06F9/3824 ,  G06F9/3842 ,  G06F12/0804

Abstract: A design structure for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of the delay stage(s) in order to alter the “harmonic” fixed-cycle loop behavior. The livelock detection logic (LDL) counts the number of flushes a particular instruction takes or the number of times an instruction re-issues without completing. The LDL then compares that number to a preset threshold number. Based on the result of the comparison, the LDL triggers the implementation of one of two different livelock resolution processes. These processes include dynamically configuring the delay queue within the processor into one of two different configurations and changing the sequence and timing of handling memory access instructions, based on the specific configuration of the delay queue.

Abstract translation: 用于解决处理器核心和存储器子系统控制器之间的接口处的活动锁定发生的设计结构。 通过在处理器内引入动态锁定检测机制（包括活动锁定检测实用程序或逻辑）来解决活锁，以检测活动锁定状态并动态地改变延迟阶段的持续时间，以便改变“谐波”固定循环回路 行为。 活动锁定检测逻辑（LDL）计算特定指令的刷新次数或指令重新发出而不完成的次数。 然后，LDL将该数字与预设的阈值数进行比较。 基于比较的结果，LDL触发了两种不同的动态锁定解析过程之一的实现。 这些过程包括基于延迟队列的具体配置，将处理器内的延迟队列动态地配置为两种不同配置之一并且改变处理存储器访问指令的顺序和定时。