Abstract:
A winch mounting kit includes a first mount that may be removably coupled to a stanchion. The first mount may have a winch is removably attached thereto such that the winch is secured on the stanchion. A second mount is provided that may be removably coupled to a horizontal support. The second mount may have the winch being removably attached thereto such that the winch is secured on the horizontal support. A third mount is provided that may be removably coupled to a vertical support. The third mount may have the winch being removably attached thereto such that the winch is secured to the vertical support.
Abstract:
In a first aspect, the invention is directed to an undercarriage for a tracked vehicle. The undercarriage includes a main frame including a frame body and an equalizer bar extending laterally on either side of a pivot connection with the frame body, a first track frame and a second track frame. A first front spherical bearing connects a first end of the equalizer bar and the front end of the first track frame. A second front spherical bearing connects a second end of the equalizer bar and the front end of the second track frame. A first rear spherical bearing connects the rear end of the main frame to the rear end of the first track frame. A second rear spherical bearing connects the rear end of the main frame to the rear end of the second track frame. The spherical bearings between the rear end of the main frame and the rear ends of the track frames permit the rear ends of the track frames to accommodate the arcuate movement of the front ends of the track frames as the equalizer bar pivots about its pivot connection when the vehicle travels over uneven terrain. The spherical bearings further on both the front and the rear of the vehicle also permit the tracks of the vehicle to more fully contact the ground when the ground is not perfectly flat. An example of such a situation may be when the vehicle travels on a road which is crowned.
Abstract:
A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.
Abstract:
A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.
Abstract:
A system and method for tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
Abstract:
A system and method for dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.
Abstract:
A container (1) for acting as a storage enclosure and launch tube for a missile (3), the container (1) comprising an integral missile efflux management system including an efflux deflector (1d) positioned for receiving the missile efflux and deflecting it into a series of ducts (8) which run alongside the missile to the missile exit end (16) of the container (1), which end may have an openable cover (7) operable to close both the missile exit and the exits from the ducts (8). The efflux deflector is a dome-shaped base-plate (1d) spaced from the ducts to define a plenum chamber. The particular interior shape of the base plate (1d) ensures optimum efflux management.
Abstract:
A modular tire lifting assembly includes a yoke that has a pair of arms which are spaced apart from each other such that t a vehicle tire can be positioned between the pair of arms. The yoke is comprised of a plurality of modular sections such that the yoke can be disassembled for storage in a vehicle. A first handle and a second handle are provided and either can be removably attachable to the yoke. Either the first handle or the second handle angles upwardly from the yoke when removably attached to the yoke thereby facilitating the yoke to lift the vehicle tire when either the first handle or the second handle is urged downwardly. Additionally, the second handle has a length that is less than a length of the first handle.
Abstract:
In a first aspect, the invention is directed to an undercarriage for a tracked vehicle. The undercarriage includes a main frame including a frame body and an equalizer bar extending laterally on either side of a pivot connection with the frame body, a first track frame and a second track frame. A first front spherical bearing connects a first end of the equalizer bar and the front end of the first track frame. A second front spherical bearing connects a second end of the equalizer bar and the front end of the second track frame. A first rear spherical bearing connects the rear end of the main frame to the rear end of the first track frame. A second rear spherical bearing connects the rear end of the main frame to the rear end of the second track frame. The spherical bearings between the rear end of the main frame and the rear ends of the track frames permit the rear ends of the track frames to accommodate the arcuate movement of the front ends of the track frames as the equalizer bar pivots about its pivot connection when the vehicle travels over uneven terrain. The spherical bearings further on both the front and the rear of the vehicle also permit the tracks of the vehicle to more fully contact the ground when the ground is not perfectly flat. An example of such a situation may be when the vehicle travels on a road which is crowned.
Abstract:
Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.