公开(公告)号：US5487041A

公开(公告)日：1996-01-23

申请号：US309823

申请日：1994-09-21

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/84 ,  G11C29/832

摘要： A cache memory device includes a plurality of memory cell arrays each including a plurality of memory cell rows, a plurality of first fuse elements each provided corresponding to each memory cell row and disconnected when the corresponding memory cell row is defective, and a plurality of second fuse elements each provided corresponding to each memory cell array and disconnected when the corresponding memory cell array is defective. As a result, the cache memory device can indicate that, when a bit line of a certain memory cell array is defective, the memory cell array is defective by disconnecting a second fuse element corresponding to the memory cell array.

摘要翻译： 高速缓冲存储器装置包括多个存储单元阵列，每个存储单元阵列包括多个存储单元行，多个第一熔丝元件，每个第一熔丝元件对应于每个存储单元行设置，并且当相应的存储单元行有缺陷时被断开;多个第二熔丝元件 每个熔丝元件对应于每个存储单元阵列，并且当对应的存储单元阵列有缺陷时断开。 结果，高速缓冲存储器件可以指示当某个存储单元阵列的位线有缺陷时，通过断开与存储单元阵列相对应的第二熔丝元件，存储单元阵列有缺陷。

公开(公告)号：US5280441A

公开(公告)日：1994-01-18

申请号：US725782

申请日：1991-07-09

申请人： Tomohisa Wada ,  Kenji Anami ,  Shuji Murakami

发明人： Tomohisa Wada ,  Kenji Anami ,  Shuji Murakami

IPC分类号： G11C11/417 ,  G11C7/18 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  H01L27/108 ,  G11C5/06

CPC分类号： H01L27/10817 ,  G11C7/18

摘要： A plurality of bit line signal IO lines L1, /L1, . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.

摘要翻译： 多个位线信号IO线L1，/ L1，...。 。 。 Ln和/ Ln布置在存储单元阵列上。 这些位线信号IO线被布置成与相应的位线BL1，/ BL1交叉。 。 。 BLn和/ BLn，分别连接到相应的位线。 每个位线信号IO线具有延伸到存储单元阵列的垂直于位线的方向的一端的端部，并且在端部耦合到位线外围电路。 尽管现有技术中位线外围电路只能位于位线的上端和下端，但位线外围电路也可以布置在本发明的位线信号IO线的端部。 这可以增加位线外围电路的布局的自由度，并且因此位线外围电路可以分散地布置在更大的区域中。

公开(公告)号：US4947374A

公开(公告)日：1990-08-07

申请号：US191115

申请日：1988-05-06

申请人： Tomohisa Wada ,  Shuji Murakami

发明人： Tomohisa Wada ,  Shuji Murakami

IPC分类号： G11C7/22 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C8/18

摘要： In a static random access memory, when address signals change, one-shot pulses are responsively generated. A detection signal obtained by ORing the one-shot pulses is employed as an equalize signal. Potentials of a bit line pair is equalized in response to the equalize signal. A write inhibiting signal having a pulse width larger than that of the equalize signal is generated by a pulse width increasing circuit. A write operation of data is inhibited in response to the write inhibiting signal.

摘要翻译： 在静态随机存取存储器中，当地址信号改变时，响应地产生单触发脉冲。 采用通过对单触发脉冲进行OR运算而获得的检测信号作为均衡信号。 位线对的电位响应均衡信号而相等。 通过脉冲宽度增加电路产生具有大于均衡信号的脉冲宽度的写禁止信号。 响应于写禁止信号，数据的写操作被禁止。

公开(公告)号：US6115280A

公开(公告)日：2000-09-05

申请号：US833178

申请日：1997-04-04

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1018

摘要： A semiconductor memory for operating in burst mode. The memory has a memory cell array divided into a plurality of memory blocks, a plurality of (e.g., 2) output registers each including a plurality of output data retaining blocks corresponding to the multiple memory blocks, and a burst counter unit. The output registers alternately receive data transferred from the memory cell array. In accordance with the result of counting by the burst counter unit, the data retained in the output registers is output alternately in bursts, whereby the speed of data read operation in the memory is boosted regardless of the operating speed of the memory cell array therein.

摘要翻译： 用于在突发模式下操作的半导体存储器。 存储器具有分成多个存储块的存储单元阵列，每个包括与多个存储块相对应的多个输出数据保持块的多个（例如，2个）输出寄存器以及突发计数器单元。 输出寄存器交替地接收从存储单元阵列传送的数据。 根据突发计数器单元的计数结果，保持在输出寄存器中的数据以脉冲串方式交替地输出，由此无论存储器单元阵列的操作速度如何，存储器中的数据读取操作的速度被提升。

公开(公告)号：US6026048A

公开(公告)日：2000-02-15

申请号：US005688

申请日：1998-01-13

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C13/00

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/00 ,  G11C2207/2218 ,  G11C2207/2245

摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

摘要翻译： 与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。 保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。 在从存储单元阵列未读出数据的期间，写入数据被锁存电路取入并保持。 比较器比较保持的内部地址信号和用于读取数据的内部地址信号。 如果它们之间发现匹配，则多路复用器从锁存电路输出数据以进行外部输出。 因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓冲存储器的高速操作，并且实现诸如超级计算机等各种级别的计算机的速度性能， 大型计算器，工作站和个人计算机可以改进。

公开(公告)号：US5959639A

公开(公告)日：1999-09-28

申请号：US695880

申请日：1996-08-12

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G06F12/08 ,  G06F3/14 ,  G06T11/00 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G06F15/167

CPC分类号： G09G5/39 ,  G06F3/1438 ,  G09G2360/121 ,  G09G5/363

摘要： In a computer graphics apparatus, a main memory stores image data representing pixels on a raster scan display. A cache memory is provided for retaining a partial copy of the image data in the main memory. A computing unit processes the image data copied into the cache memory. A video cache memory acquires image data from the main memory and the cache memory. A graphics controller acquires image data from the video cache memory and outputs the image data to the raster scan display.

摘要翻译： 在计算机图形学装置中，主存储器存储表示光栅扫描显示器上的像素的图像数据。 提供了高速缓冲存储器，用于将图像数据的部分副本保留在主存储器中。 计算单元处理复制到高速缓冲存储器中的图像数据。 视频缓存存储器从主存储器和高速缓冲存储器获取图像数据。 图形控制器从视频高速缓冲存储器获取图像数据，并将该图像数据输出到光栅扫描显示。

公开(公告)号：US5886934A

公开(公告)日：1999-03-23

申请号：US897829

申请日：1997-07-21

申请人： Hideaki Nagaoka ,  Tomohisa Wada

发明人： Hideaki Nagaoka ,  Tomohisa Wada

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051

摘要： A semiconductor memory device comprises first and second data buses. An output drive circuit adjusts the potentials at the first and second data buses in response to an internal read signal read from a memory cell. The gates of a PMOS transistor and an NMOS transistor forming an output stage corresponding to an output final stage are connected to ends of the first and second data buses, respectively. The potential of an output signal derived from the output stage loosely transits with a value decided by the capacitances of the first and second data buses. Thus, through rate control of the output signal can be implemented without reducing current drivability of the MOS transistors forming the output final stage.

摘要翻译： 半导体存储器件包括第一和第二数据总线。 输出驱动电路响应于从存储器单元读取的内部读取信号来调整第一和第二数据总线上的电位。 形成与输出末级相对应的输出级的PMOS晶体管和NMOS晶体管的栅极分别连接到第一和第二数据总线的端。 从输出级导出的输出信号的电位以由第一和第二数据总线的电容决定的值松散地转移。 因此，可以实现输出信号的速率控制，而不会降低形成输出最终级的MOS晶体管的电流驱动能力。

公开(公告)号：US5841961A

公开(公告)日：1998-11-24

申请号：US487214

申请日：1995-06-07

申请人： Kunihiko Kozaru ,  Tomohisa Wada ,  Hirotoshi Sato

发明人： Kunihiko Kozaru ,  Tomohisa Wada ,  Hirotoshi Sato

IPC分类号： G06F12/08 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00 ,  G06F11/16

CPC分类号： G11C29/80 ,  G11C29/808 ,  G11C29/848

摘要： In repairing a defective memory cell of a data memory placed in a data memory region, a repairing circuit which employs a repairing method causing some access penalty but having high repairing efficiency is located in a redundant row region and a redundant column region in the data memory region. On the other hand, in repairing a defective memory cell of a tag memory placed in a tag memory region, a repairing circuit which employs a repairing method having low repairing efficiency but causing little access penalty is located in a redundant column region in the tag memory region. Accordingly, optimal repair of a defective memory cell can be achieved according to respective functions of the tag memory and the data memory.

摘要翻译： 在修复放置在数据存储器区域中的数据存储器的有缺陷的存储单元的情况下，采用修复方法引起一些访问损失但具有高修复效率的修复电路位于数据存储器中的冗余行区域和冗余列区域中 地区。 另一方面，在修复放置在标签存储区域中的标签存储器的有缺陷的存储单元的情况下，使用维修效率低但导致小的访问损失的修复方法的修复电路位于标签存储器的冗余列区域中 地区。 因此，可以根据标签存储器和数据存储器的各自的功能来实现对缺陷存储单元的最佳修复。

公开(公告)号：US5563820A

公开(公告)日：1996-10-08

申请号：US347092

申请日：1994-11-23

申请人： Tomohisa Wada ,  Motomu Ukita

发明人： Tomohisa Wada ,  Motomu Ukita

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/407 ,  G11C29/00 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  G11C5/06

CPC分类号： G11C29/804 ,  G11C29/80 ,  G11C29/848 ,  G11C7/18 ,  H01L27/11

摘要： Bit lines which are adjacent to each other are connected to bit line signal input/output lines which are not adjacent to each other, via through holes. By this connection, data input/output lines, shield lines and a global word line are arranged between the through holes, whereby the distance between the through holes can be widened, minimum space between the bit lines can be widened, and therefore, higher integration of the memory array is realized.

摘要翻译： 彼此相邻的位线经由通孔与彼此不相邻的位线信号输入/输出线连接。 通过这种连接，数据输入/输出线，屏蔽线和全局字线布置在通孔之间，从而可以扩大通孔之间的距离，可以扩大位线之间的最小间隔，因此更高的集成度 的存储器阵列。

公开(公告)号：US5379248A

公开(公告)日：1995-01-03

申请号：US181524

申请日：1994-01-13

申请人： Tomohisa Wada ,  Kenji Anami ,  Shuji Murakami

发明人： Tomohisa Wada ,  Kenji Anami ,  Shuji Murakami

IPC分类号： G11C11/417 ,  G11C7/18 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  H01L27/108 ,  G11C5/06

CPC分类号： H01L27/10817 ,  G11C7/18

摘要： A plurality of bit line signal IO lines L1, /L1 . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.

摘要翻译： 多个位线信号IO线L1，L1。 的。 的。 Ln和/ Ln布置在存储单元阵列上。 这些位线信号IO线被布置成与相应的位线BL1，/ BL1交叉。 的。 的。 BLn和/ BLn，分别连接到相应的位线。 每个位线信号IO线具有延伸到存储单元阵列的垂直于位线的方向的一端的端部，并且在端部耦合到位线外围电路。 尽管现有技术中位线外围电路只能位于位线的上端和下端，但位线外围电路也可以布置在本发明的位线信号IO线的端部。 这可以增加位线外围电路的布局的自由度，并且因此位线外围电路可以分散地布置在更大的区域中。