公开(公告)号：US11804841B2

公开(公告)日：2023-10-31

申请号：US17569041

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin Choi ,  Yonghun Kim ,  Jinhyeok Baek ,  Yoochang Sung ,  Changsik Yoo ,  Jeongdon Ihm

IPC: H03K19/003 ,  G11C7/22 ,  G11C5/14 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/06

CPC classification number: H03K19/00384 ,  G11C5/147 ,  G11C7/22 ,  H03K19/018521 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/06

Abstract: An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

公开(公告)号：US11627021B2

公开(公告)日：2023-04-11

申请号：US17563406

申请日：2021-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi ,  Changsik Yoo

IPC: H04L25/02 ,  H04L25/14 ,  H04L25/49

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.

公开(公告)号：US11552730B2

公开(公告)日：2023-01-10

申请号：US17144425

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyongho Kim ,  Changsik Yoo ,  Kyungmin Kim

IPC: H04L1/00

Abstract: Disclosed is a transmitter which includes an encoder and a transmission interface circuit. The encoder receives data bits and generates conversion bits, a number of is the conversion bits being more than a number of the data bits, based on the number of the data bits. The encoder detects a risk pattern of the conversion bits to generate detection data and converts the risk pattern into a replacement pattern based on the detection data to generate code bits, a number of is the code bits being equal to the number of the conversion bits.

公开(公告)号：US20220351763A1

公开(公告)日：2022-11-03

申请号：US17536282

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changsik Yoo ,  Hyunah An

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/14

Abstract: A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.

公开(公告)号：US20210342151A1

公开(公告)日：2021-11-04

申请号：US17241159

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： KYOUNGHO KIM ,  Changsik Yoo ,  Baekjin Lim

IPC: G06F9/30 ,  G06F1/10 ,  G06F9/38

Abstract: A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate precoding data and a transmitter configured to transmit the precoding data through a transmission channel and a second device including an integrator configured to perform an integral on the precoding data, an integral sampler including a plurality of samplers configured to output sampling data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the precoding data and a clock based on the decoded data and an output of another one of the samplers.

公开(公告)号：US12009057B2

公开(公告)日：2024-06-11

申请号：US18143967

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US20230368855A1

公开(公告)日：2023-11-16

申请号：US18061764

申请日：2022-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyochang Kim ,  Changsik Yoo

IPC: G11C29/02 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C29/023 ,  G11C7/1012 ,  G11C7/062 ,  G11C7/22

Abstract: A memory device includes a DC conversion circuit that receives a first edge-triggered phase signal having first pulses each extending from a rising edge of a first phase signal of a multiphase clock to a later rising edge of a second phase signal of the multiphase clock and a second edge-triggered phase signal having second pulses each extending from a rising edge of the second phase signal to a later rising edge of the first phase signal, and outputting a first voltage corresponding to the first edge-triggered phase signal and a second voltage corresponding to the second edge-triggered phase signal, a comparator that compares the first voltage with the second voltage, control logic that generates a control code corresponding to an output value from the comparator, and a delay cell that delays the second phase signal according to the control code.

公开(公告)号：US20230307022A1

公开(公告)日：2023-09-28

申请号：US18143967

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US20230140230A1

公开(公告)日：2023-05-04

申请号：US18146732

申请日：2022-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyongho KIM ,  Changsik Yoo ,  Kyungmin Kim

IPC: H04L1/00

Abstract: Disclosed is a transmitter which includes an encoder and a transmission interface circuit. The encoder receives data bits and generates conversion bits, a number of is the conversion bits being more than a number of the data bits, based on the number of the data bits. The encoder detects a risk pattern of the conversion bits to generate detection data and converts the risk pattern into a replacement pattern based on the detection data to generate code bits, a number of is the code bits being equal to the number of the conversion bits.

公开(公告)号：US11615824B2

公开(公告)日：2023-03-28

申请号：US17536282

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changsik Yoo ,  Hyunah An

IPC: G11C7/22 ,  G11C5/14 ,  G11C7/10

Abstract: A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.