公开(公告)号：US20230395660A1

公开(公告)日：2023-12-07

申请号：US18100688

申请日：2023-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan KIM ,  Kyungho KIM ,  Kanghun MOON ,  Choeun LEE ,  Yonguk JEON

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device, including a fin active region; a device isolation layer covering two sidewalls of the fin active region on the substrate; a gate structure; a nano-sheet structure including a plurality of nano-sheets; and source/drain regions disposed on the fin active region and adjacent to the gate structure, wherein each source/drain region of the source/drain regions includes a buffer layer, an inner impurity layer, and a central impurity layer which are sequentially stacked, wherein the buffer layer fills a first indentation between two vertically-adjacent nano-sheets and a second indentation between the top surface of the fin active region and a nano-sheet, and wherein the plurality of nano-sheets contact side surfaces of the inner impurity layer.

公开(公告)号：US20170162674A1

公开(公告)日：2017-06-08

申请号：US15355781

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Kyung Yub JEON ,  Sujin JUNG ,  Haegeon JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

公开(公告)号：US20160087104A1

公开(公告)日：2016-03-24

申请号：US14861748

申请日：2015-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYEONGCHAN LEE ,  Nam-Kyu KIM ,  JinBum KIM ,  KWAN HEUM LEE ,  Choeun LEE ,  Sujin JUNG

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.

Abstract translation: 提供半导体器件及其制造方法。 器件可以包括从衬底突出的有源图案，与有源图案交叉的栅极结构以及设置在相邻栅极结构之间的源极/漏极区域。 源极/漏极区域可以包括凹陷区域中的源极/漏极外延层，其形成在相邻的栅极结构之间的有源图案中。 此外，可以在有源图案中提供杂质扩散区域以沿着凹陷区域的内表面包围源极/漏极外延层。