公开(公告)号：US20240063131A1

公开(公告)日：2024-02-22

申请号：US18203239

申请日：2023-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeean Lee ,  Dahee Kim ,  Taehoon Lee ,  Gyujin Choi

IPC: H01L23/538 ,  H10B80/00 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H10B80/00 ,  H01L25/18 ,  H01L25/50 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/29 ,  H01L2224/19 ,  H01L2224/211 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29194 ,  H01L2924/0665 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/33 ,  H01L2224/33181 ,  H01L2224/73267 ,  H01L2224/32221 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1441 ,  H01L2924/14335 ,  H01L23/3128

Abstract: A semiconductor package includes a first substrate having a first surface and a second surface, and having a cavity extending from the first surface to the second surface in a vertical direction, a first chip disposed in the cavity of the first substrate, a redistribution structure on the first surface of the first substrate, a second chip on the redistribution structure, a third chip spaced apart from the second chip in a horizontal direction and disposed on the redistribution structure, and a bridge chip embedded in the redistribution structure, wherein the redistribution structure includes a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern.

公开(公告)号：US11894333B2

公开(公告)日：2024-02-06

申请号：US17401664

申请日：2021-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahee Kim ,  Jeongrim Seo ,  Gookmi Song

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/214 ,  H01L2224/2105 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/3512

Abstract: A semiconductor package includes: a redistribution substrate including a connection via and a redistribution layer electrically connected to each other, and a redistribution pad electrically connected to the redistribution layer by the connection via, a space pattern separating at least some of the redistribution pads from each other, a dummy metal pattern at least partially surrounded by the space pattern, and a degassing opening passing through at least one of the redistribution pad and the dummy metal pattern; a connection bump electrically connected to the redistribution pad; and a semiconductor chip on the redistribution substrate and including a connection pad electrically connected to the redistribution layer, the redistribution pad including a plurality of protrusions protruding from the same plane in directions different from each other and having a corner having a rounded shape, and the dummy metal pattern includes branch patterns each extending in directions different from one another.