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    Semiconductor package and method of manufacturing the same
    11.
    发明授权
    Semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US12199002B2

    公开(公告)日：2025-01-14

    申请号：US17736500

    申请日：2022-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehwan Kim ,  Kyungsuk Oh ,  Jaechoon Kim

    IPC: H01L21/00 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L25/04

    Abstract: A semiconductor package includes a first semiconductor chip including first through electrodes and having a first hot zone in which the first through electrodes are disposed; a heat redistribution chip disposed on the first semiconductor chip, having a cool zone overlapping the first hot zone in a stacking direction with respect to the first semiconductor chip, and including first heat redistribution through electrodes disposed outside of an outer boundary of the cool zone and electrically connected to the first through electrodes, respectively; a second semiconductor chip disposed on the heat redistribution chip, having a second hot zone overlapping the cool zone in the stacking direction, and including second through electrodes disposed in the second hot zone and electrically connected to the first heat redistribution through electrodes, respectively; and a first thermal barrier layer disposed between the first hot zone and the cool zone, wherein the first through electrodes are electrically connected to the second through electrodes by bypassing the cool zone via the first heat redistribution through electrodes.

    Integrated circuit semiconductor device
    13.
    发明授权
    Integrated circuit semiconductor device 有权

    公开(公告)号：US12009303B2

    公开(公告)日：2024-06-11

    申请号：US17374713

    申请日：2021-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

    CPC classification number: H01L23/5286 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

    Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

    ELECTRONIC DEVICE AND METHOD FOR CONTROLLING TEMPERATURE THEREOF
    14.
    发明申请
    ELECTRONIC DEVICE AND METHOD FOR CONTROLLING TEMPERATURE THEREOF 有权
    电子设备及其温度控制方法

    公开(公告)号：US20130321041A1

    公开(公告)日：2013-12-05

    申请号：US13830651

    申请日：2013-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaechoon Kim ,  SangWook Ju ,  Eunseok Cho

    IPC: H03K3/011

    CPC classification number: H03K3/011 ,  G06F1/203 ,  G06F1/206 ,  G06F1/324 ,  G06F11/3058 ,  Y02D10/126

    Abstract: A method for controlling a temperature of an electronic device which includes a semiconductor chip is provided. The temperature control method includes measuring a temperature of a measurement point using the electronic device, comparing the temperature of the measurement point with a target temperature varying according to a period of time when the semiconductor chip operates using the electronic device, and decreasing a clock frequency of the semiconductor chip using the electronic device when the temperature of the measurement point is higher than the target temperature.

    Abstract translation: 提供了一种用于控制包括半导体芯片的电子设备的温度的方法。 温度控制方法包括使用电子装置测量测量点的温度，将测量点的温度与根据半导体芯片使用电子设备操作的时间段变化的目标温度进行比较，并且降低时钟频率 当测量点的温度高于目标温度时，使用电子器件的半导体芯片。

    INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE
    15.
    发明申请
    INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250157930A1

    公开(公告)日：2025-05-15

    申请号：US19028311

    申请日：2025-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

    Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

    HEAT DISSIPATION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    17.
    发明公开
    HEAT DISSIPATION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240321681A1

    公开(公告)日：2024-09-26

    申请号：US18505670

    申请日：2023-11-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggu Kang ,  Jaechoon Kim ,  Sungho Mun ,  Hwanjoo Park

    IPC: H01L23/46 ,  H05K7/20

    CPC classification number: H01L23/46 ,  H05K7/20327

    Abstract: Provided is a semiconductor package including a substrate, a first semiconductor device on the substrate, and a heat dissipation structure on the first semiconductor device including a heat dissipation chamber configured to provide an internal space in which a working fluid moves, and a plurality of first isolation walls arranged in the heat dissipation chamber to define a first center channel and a plurality of first vapor channels communicating with each other via the first center channel, wherein each of the plurality of first isolation walls vertically overlaps the first semiconductor device, the first center channel vertically overlaps the first semiconductor device, and each of the plurality of first vapor channels extends from the first center channel in a lateral direction.

    INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE
    18.
    发明公开
    INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240290720A1

    公开(公告)日：2024-08-29

    申请号：US18660550

    申请日：2024-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

    CPC classification number: H01L23/5286 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

    Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

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