公开(公告)号：US20250015049A1

公开(公告)日：2025-01-09

申请号：US18412447

申请日：2024-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo Park ,  Sunggu Kang ,  Jae Choon Kim ,  Taehwan Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor package includes a redistribution line structure that has a redistribution line layer. A first semiconductor chip is disposed above the redistribution line structure and includes a first region with a first thickness and a second region with a second thickness that is less than the first thickness. A sub-semiconductor package includes a second semiconductor chip and is disposed above the second region of the first semiconductor chip. A silicon through via penetrates the second region of the first semiconductor chip and electrically connects the sub-semiconductor package with the redistribution line structure. A sealant seals at least a portion of each of the first semiconductor chip and the sub-semiconductor package. The sub-semiconductor package is disposed within the second region of the first semiconductor chip.

公开(公告)号：US20240055339A1

公开(公告)日：2024-02-15

申请号：US18229039

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo Park ,  Sunggu Kang ,  Jaechoon Kim ,  Taehwan Kim ,  Sungho Mun ,  Jonggyu Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/3675 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/1435 ,  H01L2924/1431 ,  H01L2924/182

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor package on the first redistribution structure, the first semiconductor package including a first semiconductor chip which includes a first device layer and a first semiconductor substrate including a through electrode, a second semiconductor chip which is on the first semiconductor chip and includes a second device layer and a second semiconductor substrate, and a molding member surrounding the first semiconductor chip, a second redistribution structure on an upper surface of the molding member, and a second semiconductor package on the second redistribution structure, the second semiconductor package including a third semiconductor chip, wherein the second semiconductor chip is apart from the second semiconductor package in a horizontal direction, and an upper surface of the second semiconductor chip is higher than the upper surface of the molding member.

公开(公告)号：US20230395459A1

公开(公告)日：2023-12-07

申请号：US18305726

申请日：2023-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggu Kang ,  Youngdeuk Kim ,  Mina Choi

IPC: H01L23/367 ,  H01L25/16 ,  H10B80/00 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L25/162 ,  H01L25/165 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes: a first semiconductor chip on a first package substrate; a second semiconductor chip on a second package substrate; an interposer between the first semiconductor chip and the second package substrate; and a heat dissipation layer on the interposer, wherein the first and second semiconductor chips are spaced apart from each other horizontally and do not overlap in a vertical direction, and wherein a first portion of the heat dissipation layer at least partially overlapping the first semiconductor chip in the vertical direction and a second portion of the heat dissipation layer at least partially overlapping the second semiconductor chip in the vertical direction are spaced apart from each other, and the first portion is positioned around an outer boundary of the second portion.

公开(公告)号：US20240321681A1

公开(公告)日：2024-09-26

申请号：US18505670

申请日：2023-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggu Kang ,  Jaechoon Kim ,  Sungho Mun ,  Hwanjoo Park

IPC: H01L23/46 ,  H05K7/20

CPC classification number: H01L23/46 ,  H05K7/20327

Abstract: Provided is a semiconductor package including a substrate, a first semiconductor device on the substrate, and a heat dissipation structure on the first semiconductor device including a heat dissipation chamber configured to provide an internal space in which a working fluid moves, and a plurality of first isolation walls arranged in the heat dissipation chamber to define a first center channel and a plurality of first vapor channels communicating with each other via the first center channel, wherein each of the plurality of first isolation walls vertically overlaps the first semiconductor device, the first center channel vertically overlaps the first semiconductor device, and each of the plurality of first vapor channels extends from the first center channel in a lateral direction.

公开(公告)号：US20240119211A1

公开(公告)日：2024-04-11

申请号：US18206278

申请日：2023-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Ho Lee ,  Jae Choon Kim ,  Tae-Hyun Kim ,  Jeong-Hyeon Park ,  Hwanjoo Park ,  Sunggu Kang ,  Sung-Ho Mun

IPC: G06F30/392 ,  G06N20/00

CPC classification number: G06F30/392 ,  G06N20/00

Abstract: A semiconductor design optimization system that includes: a data base configured to store design data, a training data preprocessing unit configured to preprocess the design data and generate training data, a data learning unit configured to generate a physical property prediction model by training using the training data, a physical property prediction unit configured to generate predicted physical property data including information associated with predicted physical property values for each region of a semiconductor device to be fabricated, wherein the physical property prediction unit is configured to input, into the physical property prediction model, input data including information associated with design drawings of the semiconductor device to be fabricated, and a layout generator configured generate a design layout optimized to distribute the predicted physical property values for each region of the semiconductor device to be fabricated by modifying the design drawings based on the predicted physical property data.

公开(公告)号：US20240321669A1

公开(公告)日：2024-09-26

申请号：US18380854

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggu Kang ,  JAE CHOON KIM ,  SUNG-HO MUN ,  Hwanjoo Park

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/105 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32245

Abstract: A semiconductor package includes a substrate, a semiconductor die on the substrate, a heat spreader covering the semiconductor die. The heat spreader includes an upper plate portion, a base portion, and a sidewall portion connecting the upper plate portion to the base portion. The upper plate portion and the sidewall portion define an underlying cavity. The base portion is disposed on the substrate, extends from an exterior side of the sidewall portion in a horizontal direction, includes a plurality of first through holes, has a bottom surface at the same level as a bottom surface of the sidewall portion, and has a height in a vertical direction from a lowermost portion to an uppermost portion thereof less than or equal to that of the sidewall portion.