公开(公告)号：US20220068818A1

公开(公告)日：2022-03-03

申请号：US17213506

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung SONG ,  Kyoung Lim SUK ,  Jaegwon JANG ,  Wonkyoung CHOI

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.

公开(公告)号：US20210125908A1

公开(公告)日：2021-04-29

申请号：US16946209

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho JANG ,  Jongyoun KIM ,  Jungho PARK ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US20250157867A1

公开(公告)日：2025-05-15

申请号：US18883053

申请日：2024-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongkook KIM ,  Heungkyu KWON ,  Youngchul KIM ,  Choonheung LEE ,  Donghyun CHA ,  Junghwa KIM ,  Junso PAK ,  Kyounghoon LEE ,  Jaegwon JANG ,  Hangchul CHOI ,  Heejung CHOI ,  Kyojin HWANG

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/18 ,  H05K1/18 ,  H10B80/00

Abstract: A semiconductor package that includes an upper package including a first package substrate, a first semiconductor chip mounted on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a printed circuit board (PCB) on which the upper package is mounted in a central region; and a stiffener positioned on a top surface of the PCB and including an opening. A top surface of the PCB contacts a bottom surface of the stiffener in at least part of edge regions of the PCB. In the central region of the PCB and in edge regions other than the at least part of edge regions of the PCB, a top surface of the PCB is apart from the bottom surface of the stiffener in a vertical direction, and the opening of the stiffener overlaps the upper package in the vertical direction.

公开(公告)号：US20230148218A1

公开(公告)日：2023-05-11

申请号：US18153601

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho JANG ,  Jongyoun KIM ,  Jungho PARK ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/49866 ,  H01L23/49838 ,  H01L24/16 ,  H01L21/4853 ,  H01L2224/16227

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US20230026972A1

公开(公告)日：2023-01-26

申请号：US17700818

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho JANG ,  Dongkyu KIM ,  Shang-Hoon SEO ,  Jaegwon JANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package includes a lower structure and an upper redistribution layer. The lower structure includes a first bump layer, a lower redistribution layer, a semiconductor chip, a molding layer, a conductive pillar, and an under pad layer. The upper redistribution layer includes a second bump layer and second redistribution layers. The first redistribution layer includes a lower redistribution pattern including a first line part and a first via part. A width of the first via part increases in a direction toward the first line part from a bottom surface of the first via part. The second redistribution layer includes an upper redistribution pattern including a second line part and the second via part. A width of the second via part increases in a direction toward the second line part from a top surface of the second via part.

公开(公告)号：US20220293501A1

公开(公告)日：2022-09-15

申请号：US17453243

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon JANG ,  Kyoung Lim SUK ,  Minjun BAE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an insulating layer, and first, second, and third redistribution patterns disposed in the insulating layer. The first to third redistribution patterns are sequentially stacked in an upward direction and are electrically connected to each other. Each of the first to third redistribution patterns includes a wire portion that extends parallel to the top surface of the redistribution substrate. Each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate. The second redistribution pattern furthers include first fine wire patterns that are less wide than the wire portion of the second redistribution pattern.

公开(公告)号：US20130256877A1

公开(公告)日：2013-10-03

申请号：US13770936

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YoungLyong KIM ,  Jaegwon JANG

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/768 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0401 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.

Abstract translation: 提供了一种半导体封装，其包括电路基板，该电路基板包括基板焊盘，与电路基板间隔开并面向电路基板的半导体芯片，所述半导体芯片包括芯片焊盘，以及将电路基板与半导体芯片电连接的连接图案。 半导体芯片可以包括多个基本上垂直于半导体芯片的顶表面延伸的第一电路图案，以及至少一个第一通孔，其将芯片焊盘电连接到第一电路图案。 芯片焊盘可以包括与连接图案接触的第一区域和第一区域外部的第二区域，并且第一通孔可以连接到芯片焊盘的第二区域。