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公开(公告)号：US20240170408A1
公开(公告)日：2024-05-23
申请号：US18426995
申请日：2024-01-30
发明人： Inhyung SONG , Kyoung Lim SUK , Jaegwon JANG , Wonkyoung CHOI
IPC分类号： H01L23/538 , H01L23/00 , H01L23/31
CPC分类号： H01L23/5384 , H01L23/3114 , H01L23/5386 , H01L24/14
摘要： A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.
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公开(公告)号：US20210111114A1
公开(公告)日：2021-04-15
申请号：US16884212
申请日：2020-05-27
发明人： Seokhyun LEE , Jongyoun KIM , Yeonho JANG , Jaegwon JANG
IPC分类号： H01L23/498 , H01L21/48
摘要： A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.
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公开(公告)号：US20170141050A1
公开(公告)日：2017-05-18
申请号：US15293786
申请日：2016-10-14
发明人： Jaegwon JANG , Youngjae KIM , Baikwoo LEE
CPC分类号： H01L23/562 , H01L21/561 , H01L21/565 , H01L23/13 , H01L23/3121 , H01L24/13 , H01L24/16 , H01L24/97 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/97 , H01L2924/15151 , H01L2924/181 , H01L2924/3512 , H01L2924/00012 , H01L2224/81 , H01L2924/014 , H01L2924/00014
摘要： A printed circuit board includes chip regions on which semiconductor chips are mounted, and a scribe region surrounding each of the chip regions. The scribe region includes first vent holes that are configured to receive a flow of molding resin and are arranged along a first direction corresponding to a flow direction of the molding resin.
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公开(公告)号：US20240096815A1
公开(公告)日：2024-03-21
申请号：US18244739
申请日：2023-09-11
发明人： Jaegwon JANG , Inhyung SONG , Yeonho JANG
IPC分类号： H01L23/544 , H01L23/498 , H01L25/10 , H01L25/16
CPC分类号： H01L23/544 , H01L23/49822 , H01L25/105 , H01L25/16 , H01L24/48 , H01L2223/54426 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058
摘要： A semiconductor package includes: a first package substrate including a first redistribution structure; a second package substrate including a second redistribution structure; a semiconductor chip provided between the first package substrate and the second package substrate, and attached to the first package substrate; and a fiducial mark provided on the second package substrate and separated from the second redistribution structure in a plan view.
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公开(公告)号：US20220406702A1
公开(公告)日：2022-12-22
申请号：US17892215
申请日：2022-08-22
发明人： Seokhyun LEE , Jongyoun KIM , Yeonho JANG , Jaegwon JANG
IPC分类号： H01L23/498 , H01L21/48
摘要： A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.
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公开(公告)号：US20200373243A1
公开(公告)日：2020-11-26
申请号：US16671625
申请日：2019-11-01
发明人： Jaegwon JANG , lnwon O , Jongyoun KIM , Seokhyun LEE , Yeonho JANG
IPC分类号： H01L23/538 , H01L23/498 , H01L23/31 , H01L23/00 , H01L25/065
摘要： A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.
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公开(公告)号：US20230148218A1
公开(公告)日：2023-05-11
申请号：US18153601
申请日：2023-01-12
发明人： Yeonho JANG , Jongyoun KIM , Jungho PARK , Jaegwon JANG
IPC分类号： H01L23/498 , H01L21/48 , H01L23/00
CPC分类号： H01L23/49816 , H01L23/49822 , H01L21/4857 , H01L23/49866 , H01L23/49838 , H01L24/16 , H01L21/4853 , H01L2224/16227
摘要： A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.
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公开(公告)号：US20230026972A1
公开(公告)日：2023-01-26
申请号：US17700818
申请日：2022-03-22
发明人： Yeonho JANG , Dongkyu KIM , Shang-Hoon SEO , Jaegwon JANG
IPC分类号： H01L23/538 , H01L23/31 , H01L23/485 , H01L23/498 , H01L23/00
摘要： Disclosed are semiconductor packages and their fabricating methods. The semiconductor package includes a lower structure and an upper redistribution layer. The lower structure includes a first bump layer, a lower redistribution layer, a semiconductor chip, a molding layer, a conductive pillar, and an under pad layer. The upper redistribution layer includes a second bump layer and second redistribution layers. The first redistribution layer includes a lower redistribution pattern including a first line part and a first via part. A width of the first via part increases in a direction toward the first line part from a bottom surface of the first via part. The second redistribution layer includes an upper redistribution pattern including a second line part and the second via part. A width of the second via part increases in a direction toward the second line part from a top surface of the second via part.
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公开(公告)号：US20220293501A1
公开(公告)日：2022-09-15
申请号：US17453243
申请日：2021-11-02
发明人： Jaegwon JANG , Kyoung Lim SUK , Minjun BAE
IPC分类号： H01L23/498 , H01L23/00 , H01L23/31
摘要： A semiconductor package includes a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an insulating layer, and first, second, and third redistribution patterns disposed in the insulating layer. The first to third redistribution patterns are sequentially stacked in an upward direction and are electrically connected to each other. Each of the first to third redistribution patterns includes a wire portion that extends parallel to the top surface of the redistribution substrate. Each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate. The second redistribution pattern furthers include first fine wire patterns that are less wide than the wire portion of the second redistribution pattern.
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公开(公告)号：US20130256877A1
公开(公告)日：2013-10-03
申请号：US13770936
申请日：2013-02-19
发明人： YoungLyong KIM , Jaegwon JANG
IPC分类号： H01L23/498
CPC分类号： H01L23/49827 , H01L21/768 , H01L23/3192 , H01L23/49811 , H01L23/5226 , H01L24/05 , H01L24/13 , H01L2224/02125 , H01L2224/0214 , H01L2224/02145 , H01L2224/0401 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05567 , H01L2224/13021 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16238 , H01L2224/81424 , H01L2224/81447 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2224/05552
摘要： Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.
摘要翻译： 提供了一种半导体封装，其包括电路基板，该电路基板包括基板焊盘，与电路基板间隔开并面向电路基板的半导体芯片，所述半导体芯片包括芯片焊盘，以及将电路基板与半导体芯片电连接的连接图案。 半导体芯片可以包括多个基本上垂直于半导体芯片的顶表面延伸的第一电路图案，以及至少一个第一通孔，其将芯片焊盘电连接到第一电路图案。 芯片焊盘可以包括与连接图案接触的第一区域和第一区域外部的第二区域，并且第一通孔可以连接到芯片焊盘的第二区域。
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