Voltage delay compensation in a buck converter

    公开(公告)号:US11876452B2

    公开(公告)日:2024-01-16

    申请号:US17477813

    申请日:2021-09-17

    CPC classification number: H02M3/158 H02M1/0016 H02M1/15

    Abstract: A DC-DC converter including a switching buck regulator including a first power switch connected to a first power node, a second power switch connected to a second power node, a driver configured to drive the first and second power switches, an output filtering inductor connected to a node between the first and second power switches, and an output filtering capacitor connected to the output filtering inductor, a controller configured to compensate for an output signal of the switching buck regulator in a time domain using a reference voltage, and a feed forward circuit connected between the switching buck regulator and the controller, and including a first buffer, a second buffer, an RC filter, and an adder may be provided. Accordingly, the DC-DC converter can reduce a delay of a compensation circuit, improve transient response characteristics of the switching buck regulator, and further improve the performance of the DC-DC converter.

    LOW-DROPOUT REGULATOR
    12.
    发明公开

    公开(公告)号:US20230170800A1

    公开(公告)日:2023-06-01

    申请号:US17994134

    申请日:2022-11-25

    CPC classification number: H02M3/157 H03M1/44 H03M1/502 H03M1/0607

    Abstract: An LDO regulator includes a voltage-to-time converter configured to convert a fluctuation in an output voltage sensed from an output node into a time domain signal having a pulse type, and output the time domain signal, based on a clock signal; a time-to-voltage converter configured to receive the time domain signal, convert the time domain signal into a first voltage control signal performing first compensation for the output voltage, and output the first voltage control signal; an analog amplifier configured to output a second voltage control signal continuously performing second compensation for the output voltage, regardless of the clock signal; and a first pass transistor configured to drive the output voltage based on the second voltage control signal. The LDO regulator is configured to reduce the fluctuation in the output voltage, based on the first compensation and the second compensation.

    Low-dropout regulator
    13.
    发明授权

    公开(公告)号:US12259742B2

    公开(公告)日:2025-03-25

    申请号:US17994134

    申请日:2022-11-25

    Abstract: An LDO regulator includes a voltage-to-time converter configured to convert a fluctuation in an output voltage sensed from an output node into a time domain signal having a pulse type, and output the time domain signal, based on a clock signal; a time-to-voltage converter configured to receive the time domain signal, convert the time domain signal into a first voltage control signal performing first compensation for the output voltage, and output the first voltage control signal; an analog amplifier configured to output a second voltage control signal continuously performing second compensation for the output voltage, regardless of the clock signal; and a first pass transistor configured to drive the output voltage based on the second voltage control signal. The LDO regulator is configured to reduce the fluctuation in the output voltage, based on the first compensation and the second compensation.

    DC-DC BUCK CONVERTER AND OPERATING METHOD THEREOF

    公开(公告)号:US20220385186A1

    公开(公告)日:2022-12-01

    申请号:US17828829

    申请日:2022-05-31

    Abstract: A DC-DC buck converter for generating an output voltage by stepping down an input voltage includes a converting circuit including a plurality of transistors, a first capacitor, a second capacitor, and an inductor, the converting circuit being configured to form a current path that varies according to a plurality of modes and a plurality of phases; and a control circuit configured to: determine a mode of the converting circuit, from among the plurality of modes, according to a first amplitude of the input voltage and a second amplitude of the output voltage, and determine an ON/OFF state of each transistor of the plurality of transistors according to the determined mode and a phase from among the plurality of phases.

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