公开(公告)号：US10475749B2

公开(公告)日：2019-11-12

申请号：US15971253

申请日：2018-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunchul Kim

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor chip on a first substrate, a first mold layer provided on the first substrate to cover a side surface of the first semiconductor chip, a solder structure provided on the first substrate, and a second substrate provided on the solder structure. A guide receptacle is formed at one of a top surface of the first mold layer and a bottom surface of the second substrate, a first alignment protrusion is formed at the other of the top surface of the first mold layer and the bottom surface of the second substrate, and at least a portion of the first alignment protrusion is provided in the guide receptacle.

公开(公告)号：US20250070012A1

公开(公告)日：2025-02-27

申请号：US18672532

申请日：2024-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyung Lee ,  Sunchul Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/42 ,  H01L25/10

Abstract: The present disclosure relates to semiconductor packages and semiconductor package manufacturing methods. An example semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a support substrate on the first package substrate and spaced apart from a sidewall of the first semiconductor chip, a conductive filler on the support substrate, a connection bump between the support substrate and the interposer and electrically connecting the conductive filler with the interposer, and a first molding layer surrounding the sidewall of the first semiconductor chip and a sidewall of the connection bump.

公开(公告)号：US20230411259A1

公开(公告)日：2023-12-21

申请号：US18110994

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunchul Kim ,  Junwoo Park ,  Hyunggil Baek ,  Yongkwan Lee ,  Juhyung Lee

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/49833 ,  H01L24/16 ,  H01L23/3128 ,  H01L2224/16227 ,  H01L23/49822

Abstract: A semiconductor package includes: a lower substrate; a semiconductor chip disposed on the lower substrate; an upper substrate disposed on the semiconductor chip, having a lower surface facing the semiconductor chip, and including step structures disposed below the lower surface; a connection structure disposed around the semiconductor chip and connecting the lower substrate to the upper substrate; and an encapsulant filling a space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connection structure. The lower surface of the upper substrate has a first surface portion on which the step structures are disposed and a second surface portion having a step with respect to the lower surface of the step structures, and the second surface portion extends between opposite edges of the upper substrate.

公开(公告)号：US11557574B2

公开(公告)日：2023-01-17

申请号：US17369119

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyeong Seol ,  Sunchul Kim ,  Pyoungwan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/532 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

公开(公告)号：US11482507B2

公开(公告)日：2022-10-25

申请号：US16816593

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunchul Kim ,  Kyungsuk Oh ,  Taehun Kim ,  Pyoungwan Kim ,  Soohwan Lee

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.

公开(公告)号：US11437326B2

公开(公告)日：2022-09-06

申请号：US17032916

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon Oh ,  Sunchul Kim ,  Hyunki Kim

IPC: H01L21/50 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16 ,  H01L25/18 ,  H01L21/52

Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.

公开(公告)号：US11075189B2

公开(公告)日：2021-07-27

申请号：US16809837

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyeong Seol ,  Sunchul Kim ,  Pyoungwan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16 ,  H01L23/532

Abstract: A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

公开(公告)号：US20210104446A1

公开(公告)日：2021-04-08

申请号：US16908128

申请日：2020-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunchul Kim ,  Taehun Kim ,  Pyoungwan Kim

IPC: H01L23/367 ,  H01L23/31

Abstract: A packaged semiconductor device includes a package substrate, a first semiconductor device on the package substrate, and at least one second semiconductor device that extends on and partially covers the first semiconductor device. A heat dissipating insulation layer is provided as a coating on the first and second semiconductor devices. A conductive heat dissipation member is provided, which extends upwardly from the heat dissipating insulation layer and on portions of the first and second semiconductor devices. A protective member is provided on the package substrate, to cover the first and second semiconductor devices and the conductive heat dissipation member. This protective member includes a first covering portion, which covers an upper surface of the conductive heat dissipation member.

公开(公告)号：US10825774B2

公开(公告)日：2020-11-03

申请号：US16424000

申请日：2019-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon Oh ,  Sunchul Kim ,  Hyunki Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16 ,  H01L25/18 ,  H01L21/52

Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.