公开(公告)号：US20210013152A1

公开(公告)日：2021-01-14

申请号：US17032916

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon OH ,  Sunchul Kim ,  Hyunki Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16

Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.

公开(公告)号：US20240321823A1

公开(公告)日：2024-09-26

申请号：US18531883

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donguk Kwon ,  Gongmyeong Kim ,  Sunchul Kim ,  Chaein Moon ,  Hyeonrae Cho

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/83 ,  H01L21/481 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/18 ,  H10B80/00 ,  H01L24/48 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16227 ,  H01L2224/32237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: Provided is a semiconductor package with enhanced reliability and a method of manufacturing the same. The semiconductor package includes a package substrate including a body layer having a central area and a peripheral area, a first protective layer on a top surface of the body layer, and a second protective layer on the first protective layer in the peripheral area, a semiconductor chip mounted on the first protective layer in the central area in a flip-chip structure, an underfill in a gap between the first protective layer and the semiconductor chip and in a gap between the connection terminals, an interposer on the semiconductor chip, and inter-substrate connection terminals on the peripheral area of the package substrate and electrically connecting the package substrate to the interposer, where the underfill has an anchor structure extending into the first protective layer.

公开(公告)号：US20220392846A1

公开(公告)日：2022-12-08

申请号：US17887557

申请日：2022-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon OH ,  Sunchul Kim ,  Hyunki Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16

Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.

公开(公告)号：US11515262B2

公开(公告)日：2022-11-29

申请号：US17130170

申请日：2020-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyung Lee ,  Seok Geun Ahn ,  Sunchul Kim

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/373 ,  H01L23/31 ,  H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a first substrate including a first recess formed in a top surface of the first substrate, a first semiconductor chip disposed in the first recess and mounted on the first substrate, an interposer substrate disposed on the first semiconductor chip and including a second recess formed in a bottom surface of the interposer substrate, an adhesive layer disposed in the second recess and in contact with a top surface of the first semiconductor chip, a plurality of connection terminals spaced apart from the first recess and connecting the first substrate to the interposer substrate, and a molding layer disposed between the first substrate and the interposer substrate.

公开(公告)号：US11309228B2

公开(公告)日：2022-04-19

申请号：US16908128

申请日：2020-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunchul Kim ,  Taehun Kim ,  Pyoungwan Kim

IPC: H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/373

Abstract: A packaged semiconductor device includes a package substrate, a first semiconductor device on the package substrate, and at least one second semiconductor device that extends on and partially covers the first semiconductor device. A heat dissipating insulation layer is provided as a coating on the first and second semiconductor devices. A conductive heat dissipation member is provided, which extends upwardly from the heat dissipating insulation layer and on portions of the first and second semiconductor devices. A protective member is provided on the package substrate, to cover the first and second semiconductor devices and the conductive heat dissipation member. This protective member includes a first covering portion, which covers an upper surface of the conductive heat dissipation member.

公开(公告)号：US20210335756A1

公开(公告)日：2021-10-28

申请号：US17369119

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyeong Seol ,  Sunchul Kim ,  Pyoungwan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/532 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

公开(公告)号：US11257786B2

公开(公告)日：2022-02-22

申请号：US16821342

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunchul Kim ,  Kyungsuk Oh ,  Taehun Kim ,  Pyoungwan Kim

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package including a package substrate; a first semiconductor chip on the package substrate; a second semiconductor chip on an upper surface of the first semiconductor chip; an insulating layer on surfaces of the first semiconductor chip and the second semiconductor chip; a heat dissipation member on the insulating layer such that the heat dissipation member includes a region on an upper surface of the first semiconductor chip on which the second semiconductor chip is not disposed, and a region on an upper surface of the second semiconductor chip; a molding member on the package substrate and encapsulating the first semiconductor chip, the second semiconductor chip, and the heat dissipation member such that the molding member exposes at least a portion of an upper surface of the heat dissipation member; and a reinforcing member on the heat dissipation member and the molding member.

公开(公告)号：US20210375773A1

公开(公告)日：2021-12-02

申请号：US17130170

申请日：2020-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUHYUNG LEE ,  Seok Geun Ahn ,  Sunchul Kim

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L23/373 ,  H01L23/31 ,  H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a first substrate including a first recess formed in a top surface of the first substrate, a first semiconductor chip disposed in the first recess and mounted on the first substrate, an interposer substrate disposed on the first semiconductor chip and including a second recess formed in a bottom surface of the interposer substrate, an adhesive layer disposed in the second recess and in contact with a top surface of the first semiconductor chip, a plurality of connection terminals spaced apart from the first recess and connecting the first substrate to the interposer substrate, and a molding layer disposed between the first substrate and the interposer substrate.

公开(公告)号：US11133296B2

公开(公告)日：2021-09-28

申请号：US16698749

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanhee Jeong ,  Hyunki Kim ,  Junwoo Park ,  Byoung Wook Jang ,  Sunchul Kim ,  Su-Min Park ,  Pyoungwan Kim ,  Inku Kang ,  Heeyeol Kim

IPC: H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498

Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.

公开(公告)号：US10510672B2

公开(公告)日：2019-12-17

申请号：US15956414

申请日：2018-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk Kim ,  Sunchul Kim ,  Jinkyeong Seol ,  Byoung Wook Jang

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate.