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11.
公开(公告)号:US09342136B2
公开(公告)日:2016-05-17
申请号:US14292785
申请日:2014-05-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhan Ping , Robert Brennan , Jason Martineau
Abstract: Embodiments of the present inventive concept relate to systems and methods for dynamically allocating and/or redistributing thermal budget to each processor from a total processor thermal budget based on the workload of each processor. In this manner, the processor(s) having a higher workload can receive a higher thermal budget. The allocation can be dynamically adjusted over time. The individual and overall processor performance increases while efficiently allocating the total thermal budget. By dynamically sharing the total thermal budget of the system, the performance of the system as a whole is increased, thereby lowering, for example, the total cost of ownership (TCO) of datacenters.
Abstract translation: 本发明构思的实施例涉及用于基于每个处理器的工作负荷从总处理器热预算动态地分配和/或再分配热预算到每个处理器的系统和方法。 以这种方式,具有较高工作负载的处理器可以接收更高的热预算。 分配可以随时间动态调整。 个体和整体处理器性能提高,同时有效分配总体热预算。 通过动态共享系统的总体热预算,整个系统的性能提高,从而降低了数据中心的总拥有成本(TCO)。
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公开(公告)号:US20240168903A1
公开(公告)日:2024-05-23
申请号:US18424460
申请日:2024-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Fred Worley , Harry Rogers , Sreenivas Krishnan , Zhan Ping , Michael Scriber
CPC classification number: G06F13/385 , G06F13/4022 , G06F13/4282
Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.
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公开(公告)号:US20230333613A1
公开(公告)日:2023-10-19
申请号:US18213704
申请日:2023-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhan Ping , Qinling Zheng
CPC classification number: G06F1/206 , G05B13/024 , G05D23/1919 , G05D23/1934 , G06F1/3275 , G06F3/0616 , G06F3/0625 , G06F3/0629 , G06F3/0679 , H05K7/20836
Abstract: A system and method for active disturbance rejection based thermal control is configured to receive, at a first active disturbance rejection thermal control (ADRC) controller, a first temperature measurement from a first thermal zone. The ADRC controller generates a first output control signal for controlling a first cooling element, wherein the first output control signal is generated according a first estimated temperature and a first estimated disturbance calculated by a first extended state observer (ESO) of the first ADRC controller.
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公开(公告)号:US20230325288A1
公开(公告)日:2023-10-12
申请号:US18332242
申请日:2023-06-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Gunneswara R. Marripudi , Stephen G. Fischer , Zhan Ping , Indira Joshi , Harry Rogers
CPC classification number: G06F11/2025 , G06F11/2035 , G06F11/2046 , G06F11/2028 , G06F11/2094 , G06F11/201 , G06F11/2033 , G06F11/2092 , G06F13/4022 , G06F13/4282
Abstract: A computing system providing high-availability access to computing resources includes: a plurality of interfaces; a plurality of sets of computing resources, each of the sets of computing resources including a plurality of computing resources; and at least three switches, each of the switches being connected to a corresponding one of the interfaces via a host link and being connected to a corresponding one of the sets of computing resources via a plurality of resource connections, each of the switches being configured such that data traffic is distributed to remaining ones of the switches through a plurality of cross-connections between the switches if one of the switches fails.
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公开(公告)号:US11709528B2
公开(公告)日:2023-07-25
申请号:US17030193
申请日:2020-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhan Ping , Qinling Zheng
CPC classification number: G06F1/206 , G05B13/024 , G05D23/1919 , G05D23/1934 , G06F1/3275 , G06F3/0616 , G06F3/0625 , G06F3/0629 , G06F3/0679 , H05K7/20836
Abstract: A system and method for active disturbance rejection based thermal control is configured to receive, at a first active disturbance rejection thermal control (ADRC) controller, a first temperature measurement from a first thermal zone. The ADRC controller generates a first output control signal for controlling a first cooling element, wherein the first output control signal is generated according a first estimated temperature and a first estimated disturbance calculated by a first extended state observer (ESO) of the first ADRC controller.
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公开(公告)号:US20210004067A1
公开(公告)日:2021-01-07
申请号:US17030193
申请日:2020-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhan Ping , Qinling Zheng
Abstract: A system and method for active disturbance rejection based thermal control is configured to receive, at a first active disturbance rejection thermal control (ADRC) controller, a first temperature measurement from a first thermal zone. The ADRC controller generates a first output control signal for controlling a first cooling element, wherein the first output control signal is generated according a first estimated temperature and a first estimated disturbance calculated by a first extended state observer (ESO) of the first ADRC controller.
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公开(公告)号:US10776299B2
公开(公告)日:2020-09-15
申请号:US16433838
申请日:2019-06-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Fred Worley , Harry Rogers , Sreenivas Krishnan , Zhan Ping , Michael Scriber
Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.
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公开(公告)号:US10365981B2
公开(公告)日:2019-07-30
申请号:US15344438
申请日:2016-11-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Gunneswara R. Marripudi , Stephen G. Fischer , Zhan Ping , Indira Joshi , Harry Rogers
Abstract: A computing system providing high-availability access to computing resources includes: a plurality of interfaces; a plurality of sets of computing resources, each of the sets of computing resources including a plurality of computing resources; and at least three switches, each of the switches being connected to a corresponding one of the interfaces via a host link and being connected to a corresponding one of the sets of computing resources via a plurality of resource connections, each of the switches being configured such that data traffic is distributed to remaining ones of the switches through a plurality of cross-connections between the switches if one of the switches fails.
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公开(公告)号:US20180260008A1
公开(公告)日:2018-09-13
申请号:US15961782
申请日:2018-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhan Ping , Qinling Zheng
CPC classification number: G06F1/206 , G05B13/024 , G05D23/1919 , G05D23/1934 , G06F1/3275 , G06F3/0616 , G06F3/0625 , G06F3/0629 , G06F3/0679 , H05K7/20836
Abstract: A system and method for active disturbance rejection based thermal control is configured to receive, at a first active disturbance rejection thermal control (ADRC) controller, a first temperature measurement from a first thermal zone. The ADRC controller generates a first output control signal for controlling a first cooling element, wherein the first output control signal is generated according a first estimated temperature and a first estimated disturbance calculated by a first extended state observer (ESO) of the first ADRC controller.
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公开(公告)号:US09946664B2
公开(公告)日:2018-04-17
申请号:US14454309
申请日:2014-08-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ian P. Shaeffer , Zhan Ping
CPC classification number: G06F13/126 , G06F13/4022 , G06F13/4063 , G11C7/1075
Abstract: Exemplary embodiments include a socket interposer having a plurality of connectors configured to attach to a server board, the server board including: a first processor socket having a processor form factor, and a first memory associated with the first processor socket, a processor inserted into the at least first processor socket, the processor having access to the first memory, and a second processor socket having the processor form factor, and a second memory associated with the second processor socket, wherein the plurality of connectors are configured to fit the processor form factor; and a multi-modal I/O interface having a first mode and a second mode, wherein in the first mode provides processor-to-processor communication, and the second mode provides the first processor with accessibility to the second memory associated with the second processor socket.
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